kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg/dce, branch v6.18.22

drm/amdgpu: Add additional DCE6 SCL registers

2025-10-07T18:09:06+00:00

Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)") Signed-off-by: Alex Deucher

drm/amdgpu: use proper defines, shifts and masks in DCE6 code

2025-04-07T19:18:32+00:00

By replacing VGA_VSTATUS_CNTL by VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK, we also need to fix its usage in GMC6. Note: VGA_VSTATUS_CNTL's binary value was inverted in dce_6_0_sh_mask.h, so we need to invert its value where it was used. Signed-off-by: Alexandre Demers Signed-off-by: Alex Deucher

drm/amd/display: Program ACP related register

2022-07-05T20:13:18+00:00

- Setup the shift and mask of HDMI_ACP_SEND register - Program the register in hdmi stream encoder - Also update ACP register in azalia configuration Reviewed-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alan Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amdgpu/display/dc: Add ACP_DATA register

2022-06-03T20:45:01+00:00

Define ixAZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA Define AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK/SHIFT Reviewed-by: Harry Wentland Signed-off-by: Alan Liu Signed-off-by: Alex Deucher

drm/amd/display: Add HDMI_ACP_SEND register

2022-05-26T18:56:32+00:00

Define HDMI_ACP_SEND register shift/mask. Signed-off-by: Alan Liu Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling

2020-08-26T20:40:18+00:00

Properly define this register using a relative offset rather than an absolute offset and use the proper SOC15 macros to access it. It's also DCN, not DCE, so remove it from the DCE12 header. No functional change. Acked-by: Nirmoy Das Signed-off-by: Alex Deucher

drm/amdgpu: add some required DCE6 registers (v7)

2020-07-27T20:45:39+00:00

To help with the DC port. v2: add missing masks, add additional registers v3: more updates v4: fix accidently dropped changes v5: add missing nb pstate mask v6: add vblank, vline masks v7: add SCL_HORZ_FILTER_INIT regs Signed-off-by: Alex Deucher

amdgpu/gmc_v9: save/restore sdpif regs during S3

2020-02-25T16:30:42+00:00

fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM. Suggested-by: Alex Deucher Signed-off-by: Shirish S Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amd: Add dce-12.1 gpio aux registers (v2)

2018-05-17T15:13:19+00:00

Updating dce12 register headers by adding dc registers required for potential DP LTTPR support. v2: fix mode change Acked-by: Christian König Signed-off-by: Roman Li Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/include:cleanup vega10 dce header files.

2017-12-06T17:48:18+00:00

Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h. Signed-off-by: Feifei Xu Reviewed-by: Christian König Signed-off-by: Alex Deucher