<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg/dce, branch v5.19</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v5.19</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v5.19'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2022-05-26T18:56:32+00:00</updated>
<entry>
<title>drm/amd/display: Add HDMI_ACP_SEND register</title>
<updated>2022-05-26T18:56:32+00:00</updated>
<author>
<name>Alan Liu</name>
<email>HaoPing.Liu@amd.com</email>
</author>
<published>2022-05-17T14:30:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6880ed280edf292c542aa87567547ffb9c222597'/>
<id>urn:sha1:6880ed280edf292c542aa87567547ffb9c222597</id>
<content type='text'>
Define HDMI_ACP_SEND register shift/mask.

Signed-off-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling</title>
<updated>2020-08-26T20:40:18+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-08-18T23:24:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f8646661f713fb7d33ebe404d418bd3fa55c383e'/>
<id>urn:sha1:f8646661f713fb7d33ebe404d418bd3fa55c383e</id>
<content type='text'>
Properly define this register using a relative offset rather
than an absolute offset and use the proper SOC15 macros to
access it.  It's also DCN, not DCE, so remove it from the
DCE12 header.

No functional change.

Acked-by: Nirmoy Das &lt;nirmoy.das@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add some required DCE6 registers (v7)</title>
<updated>2020-07-27T20:45:39+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-06-22T21:06:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6863660d72e4fde650658acc10e4558ec1a277fb'/>
<id>urn:sha1:6863660d72e4fde650658acc10e4558ec1a277fb</id>
<content type='text'>
To help with the DC port.

v2: add missing masks, add additional registers
v3: more updates
v4: fix accidently dropped changes
v5: add missing nb pstate mask
v6: add vblank, vline masks
v7: add SCL_HORZ_FILTER_INIT regs

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu/gmc_v9: save/restore sdpif regs during S3</title>
<updated>2020-02-25T16:30:42+00:00</updated>
<author>
<name>Shirish S</name>
<email>shirish.s@amd.com</email>
</author>
<published>2020-01-27T11:05:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a3ed353cf8015ba84a0407a5dc3ffee038166ab0'/>
<id>urn:sha1:a3ed353cf8015ba84a0407a5dc3ffee038166ab0</id>
<content type='text'>
fixes S3 issue with IOMMU + S/G  enabled @ 64M VRAM.

Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Shirish S &lt;shirish.s@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd: Add dce-12.1 gpio aux registers (v2)</title>
<updated>2018-05-17T15:13:19+00:00</updated>
<author>
<name>Roman Li</name>
<email>Roman.Li@amd.com</email>
</author>
<published>2018-02-14T22:20:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d82420b56a17d5b39579bc46f8dad757be684f94'/>
<id>urn:sha1:d82420b56a17d5b39579bc46f8dad757be684f94</id>
<content type='text'>
Updating dce12 register headers by adding dc registers
required for potential DP LTTPR support.

v2: fix mode change

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include:cleanup vega10 dce header files.</title>
<updated>2017-12-06T17:48:18+00:00</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-11-23T10:18:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=135d4b10d3b64a4b2a77118961ed288c1a88def3'/>
<id>urn:sha1:135d4b10d3b64a4b2a77118961ed288c1a88def3</id>
<content type='text'>
Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h.

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add DP audio support for si dce6 (v3)</title>
<updated>2017-05-24T21:39:58+00:00</updated>
<author>
<name>Xiaojie Yuan</name>
<email>Xiaojie.Yuan@amd.com</email>
</author>
<published>2017-02-19T11:56:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4caca70668b777649cf64c652bc1d506a74052c6'/>
<id>urn:sha1:4caca70668b777649cf64c652bc1d506a74052c6</id>
<content type='text'>
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names
v3: fix num_pins for tahiti, pitcairn, verde and oland

Signed-off-by: Xiaojie Yuan &lt;Xiaojie.Yuan@amd.com&gt;
Reviewed-by: Edward O'Callaghan &lt;funfunctor@folklore1984.net&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register defines</title>
<updated>2017-01-27T16:12:44+00:00</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2016-11-28T22:00:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=33503e9e5a5a0ba64ce1e5a4115ec32a6a026fe4'/>
<id>urn:sha1:33503e9e5a5a0ba64ce1e5a4115ec32a6a026fe4</id>
<content type='text'>
This is required for DP HBR2 test pattern

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Add HDMI_DATA_SCRAMBLE register definition</title>
<updated>2017-01-27T16:12:43+00:00</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2016-11-28T21:30:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8c27f5c1fda5e06405d9c3092735fbc5ec2b1dfa'/>
<id>urn:sha1:8c27f5c1fda5e06405d9c3092735fbc5ec2b1dfa</id>
<content type='text'>
This is required by HDMI 2.0

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux</title>
<updated>2016-12-13T17:35:09+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2016-12-13T17:35:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9439b3710df688d853eb6cb4851256f2c92b1797'/>
<id>urn:sha1:9439b3710df688d853eb6cb4851256f2c92b1797</id>
<content type='text'>
Pull drm updates from Dave Airlie:
 "This is the main pull request for drm for 4.10 kernel.

  New drivers:
   - ZTE VOU display driver (zxdrm)
   - Amlogic Meson Graphic Controller GXBB/GXL/GXM SoCs (meson)
   - MXSFB support (mxsfb)

  Core:
   - Format handling has been reworked
   - Better atomic state debugging
   - drm_mm leak debugging
   - Atomic explicit fencing support
   - fbdev helper ops
   - Documentation updates
   - MST fbcon fixes

  Bridge:
   - Silicon Image SiI8620 driver

  Panel:
   - Add support for new simple panels

  i915:
   - GVT Device model
   - Better HDMI2.0 support on skylake
   - More watermark fixes
   - GPU idling rework for suspend/resume
   - DP Audio workarounds
   - Scheduler prep-work
   - Opregion CADL handling
   - GPU scheduler and priority boosting

  amdgfx/radeon:
   - Support for virtual devices
   - New VM manager for non-contig VRAM buffers
   - UVD powergating
   - SI register header cleanup
   - Cursor fixes
   - Powermanagement fixes

  nouveau:
   - Powermangement reworks for better voltage/clock changes
   - Atomic modesetting support
   - Displayport Multistream (MST) support.
   - GP102/104 hang and cursor fixes
   - GP106 support

  hisilicon:
   - hibmc support (BMC chip for aarch64 servers)

  armada:
   - add tracing support for overlay change
   - refactor plane support
   - de-midlayer the driver

  omapdrm:
   - Timing code cleanups

  rcar-du:
   - R8A7792/R8A7796 support
   - Misc fixes.

  sunxi:
   - A31 SoC display engine support

  imx-drm:
   - YUV format support
   - Cleanup plane atomic update

  mali-dp:
   - Misc fixes

  dw-hdmi:
   - Add support for HDMI i2c master controller

  tegra:
   - IOMMU support fixes
   - Error handling fixes

  tda998x:
   - Fix connector registration
   - Improved robustness
   - Fix infoframe/audio compliance

  virtio:
   - fix busid issues
   - allocate more vbufs

  qxl:
   - misc fixes and cleanups.

  vc4:
   - Fragment shader threading
   - ETC1 support
   - VEC (tv-out) support

  msm:
   - A5XX GPU support
   - Lots of atomic changes

  tilcdc:
   - Misc fixes and cleanups.

  etnaviv:
   - Fix dma-buf export path
   - DRAW_INSTANCED support
   - fix driver on i.MX6SX

  exynos:
   - HDMI refactoring

  fsl-dcu:
   - fbdev changes"

* tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux: (1343 commits)
  drm/nouveau/kms/nv50: fix atomic regression on original G80
  drm/nouveau/bl: Do not register interface if Apple GMUX detected
  drm/nouveau/bl: Assign different names to interfaces
  drm/nouveau/bios/dp: fix handling of LevelEntryTableIndex on DP table 4.2
  drm/nouveau/ltc: protect clearing of comptags with mutex
  drm/nouveau/gr/gf100-: handle GPC/TPC/MPC trap
  drm/nouveau/core: recognise GP106 chipset
  drm/nouveau/ttm: wait for bo fence to signal before unmapping vmas
  drm/nouveau/gr/gf100-: FECS intr handling is not relevant on proprietary ucode
  drm/nouveau/gr/gf100-: properly ack all FECS error interrupts
  drm/nouveau/fifo/gf100-: recover from host mmu faults
  drm: Add fake controlD* symlinks for backwards compat
  drm/vc4: Don't use drm_put_dev
  drm/vc4: Document VEC DT binding
  drm/vc4: Add support for the VEC (Video Encoder) IP
  drm: Add TV connector states to drm_connector_state
  drm: Turn DRM_MODE_SUBCONNECTOR_xx definitions into an enum
  drm/vc4: Fix -&gt;clock_select setting for the VEC encoder
  drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well
  drm/amdgpu: use pin rather than pin_restricted in a few cases
  ...
</content>
</entry>
</feed>
