kernel/linux.git/drivers/gpu/drm/amd/display, branch v5.4.146

drm/amd/display: Fix Dynamic bpp issue with 8K30 with Navi 1X

2021-08-26T12:36:15+00:00

[ Upstream commit 06050a0f01dbac2ca33145ef19a72041206ea983 ] Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by the number of pipes ODM Combined. How: Set MASTER_UPDATE_LOCK_DB_X to the value that is adjusted by the number of pipes ODM Combined. Reviewed-by: Martin Leung Acked-by: Aurabindo Pillai Signed-off-by: Bing Guo Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Reject non-zero src_y and src_x for video planes

2021-07-19T06:53:15+00:00

commit c6c6a712199ab355ce333fa5764a59506bb107c1 upstream. [Why] This hasn't been well tested and leads to complete system hangs on DCN1 based systems, possibly others. The system hang can be reproduced by gesturing the video on the YouTube Android app on ChromeOS into full screen. [How] Reject atomic commits with non-zero drm_plane_state.src_x or src_y values. v2: - Add code comment describing the reason we're rejecting non-zero src_x and src_y - Drop gerrit Change-Id - Add stable CC - Based on amd-staging-drm-next v3: removed trailing whitespace Signed-off-by: Harry Wentland Cc: stable@vger.kernel.org Cc: nicholas.kazlauskas@amd.com Cc: amd-gfx@lists.freedesktop.org Cc: alexander.deucher@amd.com Cc: Roman.Li@amd.com Cc: hersenxs.wu@amd.com Cc: danny.wang@amd.com Reviewed-by: Nicholas Kazlauskas Acked-by: Christian König Reviewed-by: Hersen Wu Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/display: fix incorrrect valid irq check

2021-07-19T06:53:14+00:00

commit e38ca7e422791a4d1c01e56dbf7f9982db0ed365 upstream. valid DAL irq should be < DAL_IRQ_SOURCES_NUMBER. Signed-off-by: Guchun Chen Reviewed-and-tested-by: Evan Quan Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

drm/amd/display: Verify Gamma & Degamma LUT sizes in amdgpu_dm_atomic_check

2021-07-19T06:53:10+00:00

[ Upstream commit 03fc4cf45d30533d54f0f4ebc02aacfa12f52ce2 ] For each CRTC state, check the size of Gamma and Degamma LUTs so unexpected and larger sizes wouldn't slip through. TEST: IGT:kms_color::pipe-invalid-gamma-lut-sizes v2: fix assignments in if clauses, Mark's email. Reviewed-by: Harry Wentland Signed-off-by: Mark Yacoub Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7

2021-07-19T06:53:10+00:00

[ Upstream commit 3577e1678772ce3ede92af3a75b44a4b76f9b4ad ] [WHY] DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back. Signed-off-by: Wesley Chalmers Reviewed-by: Dmytro Laktyushkin Acked-by: Stylon Wang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Release MST resources on switch from MST to SST

2021-07-19T06:53:10+00:00

[ Upstream commit 3f8518b60c10aa96f3efa38a967a0b4eb9211ac0 ] [why] When OS overrides training link training parameters for MST device to SST mode, MST resources are not released and leak of the resource may result crash and incorrect MST discovery during following hot plugs. [how] Retaining sink object to be reused by SST link and releasing MST resources. Signed-off-by: Vladimir Stempen Reviewed-by: Wenjing Liu Acked-by: Stylon Wang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Update scaling settings on modeset

2021-07-19T06:53:10+00:00

[ Upstream commit c521fc316d12fb9ea7b7680e301d673bceda922e ] [Why] We update scaling settings when scaling mode has been changed. However when changing mode from native resolution the scaling mode previously set gets ignored. [How] Perform scaling settings update on modeset. Signed-off-by: Roman Li Reviewed-by: Nicholas Kazlauskas Acked-by: Stylon Wang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: fix use_max_lb flag for 420 pixel formats

2021-07-19T06:53:08+00:00

[ Upstream commit 8809a7a4afe90ad9ffb42f72154d27e7c47551ae ] Right now the flag simply selects memory config 0 when flag is true however 420 modes benefit more from memory config 3. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Aric Cyr Acked-by: Stylon Wang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Allow bandwidth validation for 0 streams.

2021-06-18T07:58:59+00:00

[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ] [Why] Bandwidth calculations are triggered for non zero streams, and in case of 0 streams, these calculations were skipped with pstate status not being updated. [How] As the pstate status is applicable for non zero streams, check added for allowing 0 streams inline with dcn internal bandwidth validations. Signed-off-by: Bindu Ramamurthy Reviewed-by: Roman Li Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Disconnect non-DP with no EDID

2021-06-03T06:59:12+00:00

[ Upstream commit 080039273b126eeb0185a61c045893a25dbc046e ] [Why] Active DP dongles return no EDID when dongle is connected, but VGA display is taken out. Current driver behavior does not remove the active display when this happens, and this is a gap between dongle DTP and dongle behavior. [How] For active DP dongles and non-DP scenario, disconnect sink on detection when no EDID is read due to timeout. Signed-off-by: Chris Park Reviewed-by: Nicholas Kazlauskas Acked-by: Stylon Wang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin