kernel/linux.git/drivers/gpu/drm/amd/display/include, branch v6.6.132

drm/amd/display: add more cyan skillfish devices

2025-11-24T09:29:24+00:00

[ Upstream commit 3cf06bd4cf2512d564fdb451b07de0cebe7b138d ] Add PCI IDs to support display probe for cyan skillfish family of SOCs. Acked-by: Harry Wentland Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Revert Avoid overflow assignment

2024-10-10T09:58:09+00:00

commit e80f8f491df873ea2e07c941c747831234814612 upstream. This reverts commit a15268787b79 ("drm/amd/display: Avoid overflow assignment in link_dp_cts") Due to regression causing DPMS hang. Reviewed-by: Alex Hung Signed-off-by: Gabe Teeger Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/display: Avoid overflow assignment in link_dp_cts

2024-10-10T09:57:36+00:00

[ Upstream commit a15268787b79fd183dd526cc16bec9af4f4e49a1 ] sampling_rate is an uint8_t but is assigned an unsigned int, and thus it can overflow. As a result, sampling_rate is changed to uint32_t. Similarly, LINK_QUAL_PATTERN_SET has a size of 2 bits, and it should only be assigned to a value less or equal than 4. This fixes 2 INTEGER_OVERFLOW issues reported by Coverity. Signed-off-by: Alex Hung Reviewed-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Send DP_TOTAL_LTTPR_CNT during detection if LTTPR is present

2024-07-05T07:34:03+00:00

commit 2ec6c7f802332d1eff16f03e7c757f1543ee1183 upstream. [WHY] New register field added in DP2.1 SCR, needed for auxless ALPM [HOW] Echo value read from 0xF0007 back to sink Reviewed-by: Wenjing Liu Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Alex Hung Signed-off-by: Michael Strauss Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/display: get dprefclk ss info from integration info table

2024-01-20T10:51:46+00:00

[ Upstream commit 51e7b64690776a9981355428b537af9048308a95 ] [why & how] we have two SSC_En: we get ssc_info from dce_info for MPLL_SSC_EN. we used to call VBIOS cmdtbl's smu_info's SS persentage for DPRECLK SS info, is used for DP AUDIO and VBIOS' smu_info table was from systemIntegrationInfoTable. since dcn35 VBIOS removed smu_info, driver need to use integrationInfotable directly. Reviewed-by: Nicholas Kazlauskas Acked-by: Wayne Lin Signed-off-by: Charlene Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Add vendor Id for reference

2023-08-07T21:14:09+00:00

Add a new vendor ID code for reference Reviewed-by: Wenjing Liu Acked-by: Tom Chung Signed-off-by: Mike Hsieh Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Read replay data from sink

2023-08-07T21:14:07+00:00

Read DP_SINK_PR_PIXEL_DEVIATION_PER_LINE and DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Add structs for Freesync Panel Replay

2023-08-07T21:12:49+00:00

In some instances, the GPU is transmitting repeated frame to the sink without any updates or changes in the content. These repeat transmission are wasteful, resulting in power draw in different aspects of the system 1. DCN is fetching the frame of data from DF/UMC/DRAM. This memory traffic prevents power down of parts of this HW path. 2. GPU is transmitting pixel data to the display through the main link of the DisplayPort interface. This prevents power down of both the Source transmitter (TX) and the Sink receiver (RX) The concepts of utilizing replay is similar to PSR, but there is a benefit of: Source and Sink remaining synchronized which allows for - lower latency when switching from replay to live frames - enable the possibility of more use cases - easy control of the sink's refresh rate during replay Due to Source and Sink remaining timing synchronized, Replay can be activated in more UI scenarios. Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Update 128b/132b downspread factor to 0.3%

2023-07-18T15:15:05+00:00

[Why] Updating downspread factor to 0.3% to add additional margin to account for potential link rate deviations (up to 300ppm as per the DP spec). Reviewed-by: Wenjing Liu Acked-by: Alan Liu Signed-off-by: George Shen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: fix compilation error due to shifting negative value

2023-06-09T16:38:19+00:00

Currently compiling linux-next with allmodconfig triggers the following error: ./drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h: In function ‘dc_fixpt_truncate’: ./drivers/gpu/drm/amd/amdgpu/../display/include/fixed31_32.h:528:22: error: left shift of negative value [-Werror=shift-negative-value] 528 | arg.value &= (~0LL) << (FIXED31_32_BITS_PER_FRACTIONAL_PART - frac_bits); | ^~ Use `unsigned long long` instead. Signed-off-by: GONG, Ruiqi Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher