kernel/linux.git/drivers/gpu/drm/amd/display/dmub, branch v6.12.80

drm/amd/display: Update DMCUB loading sequence for DCN3.5

2025-08-20T16:30:39+00:00

[ Upstream commit d42b2331e158fa6bcdc89e4c8c470dc5da20be1f ] [Why] New sequence from HW for reset and firmware reloading has been provided that aims to stabilize the reload sequence in the case the firmware is hung or has outstanding requests. [How] Update the sequence to remove the DMUIF reset and the redundant writes in the release. Reviewed-by: Ovidiu Bunea Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Support multiple options during psr entry.

2025-05-29T09:02:53+00:00

[ Upstream commit 3a5fa55455db6a11248a25f24570c365f9246144 ] [WHY] Some panels may not handle idle pattern properly during PSR entry. [HOW] Add a condition to allow multiple options on power down sequence during PSR1 entry. Reviewed-by: Anthony Koo Signed-off-by: Martin Tsai Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fix DMUB reset sequence for DCN401

2025-05-29T09:02:29+00:00

[ Upstream commit 0dfcc2bf269010a6e093793034c048049a40ee93 ] [WHY] It should no longer use DMCUB_SOFT_RESET as it can result in the memory request path becoming desynchronized. [HOW] To ensure robustness in the reset sequence: 1) Extend timeout on the "halt" command sent via gpint, and check for controller to enter "wait" as a stronger guarantee that there are no requests to memory still in flight. 2) Remove usage of DMCUB_SOFT_RESET 3) Rely on PSP to reset the controller safely Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Ensure DMCUB idle before reset on DCN31/DCN35

2025-05-29T09:02:29+00:00

[ Upstream commit c707ea82c79dbd1d295ec94cc6529a5248c77757 ] [Why] If we soft reset before halt finishes and there are outstanding memory transactions then the memory interface may produce unexpected results, such as out of order transactions when the firmware next runs. These can manifest as random or unexpected load/store violations. [How] Increase the timeout before soft reset to ensure the DMCUB has quiesced. This is effectively 1s maximum based on experimentation. Use the enable bit check on DCN31 like we're doing on DCN35 and reorder the reset writes to follow the HW programming guide. Ensure we're reading SCRATCH7 instead of SCRATCH8 for the HALT code. No current versions of DMCUB firmware use the SCRATCH8 boot bit to dynamically switch where the HALT code goes to maintain backwards compatibility with PSP. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Full exit out of IPS2 when all allow signals have been cleared

2024-12-14T19:03:46+00:00

[ Upstream commit 0fe33e115fec305c35c66b78ad26e3755ab54b9c ] [Why] A race condition occurs between cursor movement and vertical interrupt control thread from OS, with both threads trying to exit IPS2. Vertical interrupt control thread clears the prev driver allow signal while not fully finishing the IPS2 exit process. [How] We want to detect all the allow signals have been cleared before we perform the full exit. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Leo Chen Signed-off-by: Roman Li Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Restructure dpia link training

2024-09-18T20:15:07+00:00

[WHY] We intend to consolidate dp tunneling and conventional dp link training. [HOW] 1. Use the same link training entry for both dp and dpia 2. Move SET_CONFIG of non-transparent mode to dmub side 3. Add set_tps_notification dmub_cmd to notify tps request for non-transparent dpia link training 4. Check dpcd request result and abort link training early if dpia aux tunneling fails 5. Add option to avoid affect old product 6. Separately handle wait_time_microsec for dpia Reviewed-by: Cruise Hung Reviewed-by: George Shen Reviewed-by: Meenakshikumar Somasundaram Signed-off-by: Peichen Huang Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: 3.2.299

2024-09-02T15:40:09+00:00

This version brings along the following: - DCN35 fixes - DML2 fixes - IPS fixes - ODM fixes - Miscellaneous cleanups - MST fixes - SPL fixes Acked-by: Aurabindo Pillai Signed-off-by: Aric Cyr Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Notify DMCUB of D0/D3 state

2024-08-27T21:53:51+00:00

[Why] We want to avoid arming the HPD timer in firmware when preparing for S0i3 entry when DC is considered in D3. [How] Notify DMCUB of the power state transitions so it can decide to arm the HPD timer for idle in DCN35 only in D0. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Remove unused fields from dmub_cmd_update_dirty_rect_data

2024-08-06T15:11:00+00:00

Drop coasting_vtotal_high and pad from dmub_cmd_update_dirty_rect_data, since it is not used. Acked-by: Tom Chung Signed-off-by: Rodrigo Siqueira Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add logs for debugging outbox

2024-07-27T21:35:33+00:00

The DP tunnel AUX reply is received through Outbox1. Print the Outbox1 status if an issue occurs. Signed-off-by: Cruise Reviewed-by: Nicholas Kazlauskas Reviewed-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher