<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dmub/src, branch v6.3</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-01-31T19:03:36+00:00</updated>
<entry>
<title>drm/amd/display: Reset DMUB mailbox SW state after HW reset</title>
<updated>2023-01-31T19:03:36+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2023-01-20T16:14:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4b0b4c17f5f6d4df40f2f79068909236858d61e0'/>
<id>urn:sha1:4b0b4c17f5f6d4df40f2f79068909236858d61e0</id>
<content type='text'>
[Why]
Otherwise we can be out of sync with what's in the hardware, leading
to us rerunning every command that's presently in the ringbuffer.

[How]
Reset software state for the mailboxes in hw_reset callback.
This is already done as part of the mailbox init in hw_init, but we
do need to remember to reset the last cached wptr value as well here.

Reviewed-by: Hansen Dsouza &lt;hansen.dsouza@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Update dmub header to match DMUB</title>
<updated>2023-01-13T19:59:41+00:00</updated>
<author>
<name>Mustapha Ghaddar</name>
<email>mghaddar@amd.com</email>
</author>
<published>2022-12-12T19:30:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8af54c61ccec875473e0636934ee578fa23fceb1'/>
<id>urn:sha1:8af54c61ccec875473e0636934ee578fa23fceb1</id>
<content type='text'>
[WHY]
Last PR missed name of a struct to match in DMUB

[HOW]
Update the logic in dmub_cmh.h header

Tested-by: Daniel Wheeler &lt;Daniel.Wheeler@amd.com&gt;
Reviewed-by: Meenakshikumar Somasundaram &lt;Meenakshikumar.Somasundaram@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Mustapha Ghaddar &lt;mghaddar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Update BW alloc after new DMUB logic</title>
<updated>2023-01-13T19:56:15+00:00</updated>
<author>
<name>Mustapha Ghaddar</name>
<email>mghaddar@amd.com</email>
</author>
<published>2022-12-07T19:01:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=857aa2beda3789a36de8b0c1beb6104f3e377ab2'/>
<id>urn:sha1:857aa2beda3789a36de8b0c1beb6104f3e377ab2</id>
<content type='text'>
[WHY]
After introducing new DPIA NOTIFICATION we will need
to update the exiting BW allocation logic

[HOW]
Updated the BW alloc source and header files

Tested-by: Daniel Wheeler &lt;Daniel.Wheeler@amd.com&gt;
Reviewed-by: Meenakshikumar Somasundaram &lt;Meenakshikumar.Somasundaram@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Mustapha Ghaddar &lt;mghaddar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DPIA NOTIFICATION logic</title>
<updated>2022-12-15T17:18:18+00:00</updated>
<author>
<name>Mustapha Ghaddar</name>
<email>mghaddar@amd.com</email>
</author>
<published>2022-12-01T18:00:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=669018a9929c61cb14ea374ee93df24242a7794d'/>
<id>urn:sha1:669018a9929c61cb14ea374ee93df24242a7794d</id>
<content type='text'>
[WHY]
Adding the new DPIA NOTIFY packets from DMUB
As per the design with Cruise to account for
250ms response delay otherwise

[HOW]
Added th DPIA NOTIFY logic as per DMUB logic

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Mustapha Ghaddar &lt;mghaddar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Display does not light up after S4 resume</title>
<updated>2022-10-10T21:32:55+00:00</updated>
<author>
<name>Meenakshikumar Somasundaram</name>
<email>meenakshikumar.somasundaram@amd.com</email>
</author>
<published>2022-09-30T03:55:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6f4f8ff567c48823f8279206e236643e8e8f377e'/>
<id>urn:sha1:6f4f8ff567c48823f8279206e236643e8e8f377e</id>
<content type='text'>
[Why]
Dpia hpd interrupt processing is disabled when entering S4/S0i3 and
would be reenabled after detection completes during resuming. Because,
keeping hpd interrupts enabled during detection leads to multiple
detections for the same hpd transition. There is a S4 case where dpia
hpd interrupt is missed when driver is in transitioning from hpd
interrupt processing disable to enable and the display does not light
up.

[How]
- Added dmub inbox command DMUB_CMD__DPIA_HPD_INT_ENABLE to explicitly
control dmub to issue dpia hpd interrupt or not. If dpia hpd interrupt
is disabled, dmub will keep the hpd pending and post it once driver
reenables dpia hpd interrupt or when querying with
DMUB_CMD__QUERY_HPD_STATE.
- Added dmub boot option dpia_hpd_int_enable_supported to notify dmub
about whether DMUB_CMD__DPIA_HPD_INT_ENABLE command would be used.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Mustapha Ghaddar &lt;Mustapha.Ghaddar@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DMUB support for DCN314</title>
<updated>2022-07-14T00:57:05+00:00</updated>
<author>
<name>Roman Li</name>
<email>roman.li@amd.com</email>
</author>
<published>2022-06-28T22:38:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=cc35e75273fcf4fb4f12f9d8fd979be7aa808041'/>
<id>urn:sha1:cc35e75273fcf4fb4f12f9d8fd979be7aa808041</id>
<content type='text'>
Initialize DMUB for DCN 3.1.4.
Use same funcs as DCN31.

Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: cleaning up smu_if to add future flexibility</title>
<updated>2022-06-03T20:45:01+00:00</updated>
<author>
<name>Martin Leung</name>
<email>Martin.Leung@amd.com</email>
</author>
<published>2022-02-21T02:44:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=80fb7a409c64ef304e4040320e87dbb2f10968ca'/>
<id>urn:sha1:80fb7a409c64ef304e4040320e87dbb2f10968ca</id>
<content type='text'>
This commit cleans up code that uses old variables and adds some SMU
interfaces for future flexibility.

Signed-off-by: Martin Leung &lt;Martin.Leung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Ensure that DMCUB fw in use is loaded by DC and not VBIOS</title>
<updated>2022-06-03T20:44:15+00:00</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2022-04-14T20:57:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9fe5d08fc8230adb64128986ee4af267a54e56dd'/>
<id>urn:sha1:9fe5d08fc8230adb64128986ee4af267a54e56dd</id>
<content type='text'>
[Why?]
On wake from S3/S4, driver checks if DMUB is initialized. On S4 VBIOS loads
DMUB, and driver does not reload as it appears to be initialized already.

[How?]
Add a check for the DAL_FW bit to ensure that loaded FW is from driver and
not VBIOS.

Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Reviewed-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DMCUB source files and changes for DCN32/321</title>
<updated>2022-06-03T20:43:37+00:00</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2022-02-21T21:03:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ac2e555e0a7fe571d46f7dcb1529b4bee00095d6'/>
<id>urn:sha1:ac2e555e0a7fe571d46f7dcb1529b4bee00095d6</id>
<content type='text'>
DMCUB is the display engine microcontroller which aids in modesetting
and other display related features.

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix DMUB outbox trace in S4 (#4465)</title>
<updated>2022-06-01T19:56:48+00:00</updated>
<author>
<name>Hung, Cruise</name>
<email>Cruise.Hung@amd.com</email>
</author>
<published>2022-05-13T01:16:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6ecf9773a5030aa4932096754bacff20e1b944b8'/>
<id>urn:sha1:6ecf9773a5030aa4932096754bacff20e1b944b8</id>
<content type='text'>
[Why]
DMUB Outbox0 read/write pointer not sync after resumed from S4.
And that caused old traces were sent to outbox.

[How]
Disable DMUB Outbox0 interrupt
and clear DMUB Outbox0 read/write pointer when resumes from S4.
And then enable Outbox0 interrupt before starts DMCUB.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Cruise Hung &lt;Cruise.Hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
