kernel/linux.git/drivers/gpu/drm/amd/display/dc, branch v6.0.14

drm/amd/display: fix array index out of bound error in DCN32 DML

2022-12-14T10:40:54+00:00

commit aeffc8fb2174f017a10df114bc312f899904dc68 upstream. [Why&How] LinkCapacitySupport array is indexed with the number of voltage states and not the number of max DPPs. Fix the error by changing the array declaration to use the correct (larger) array size of total number of voltage states. Signed-off-by: Aurabindo Pillai Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.0.x Signed-off-by: Greg Kroah-Hartman

drm/amd/display: Use new num clk levels struct for max mclk index

2022-12-14T10:40:49+00:00

[ Upstream commit e667ee3b0c049bf0c69426879586a2572bb28d26 ] [WHY?] When calculating watermark and dlg values, the max mclk level index and associated speed are needed to find the correlated dummy latency value. Currently the incorrect index is given due to a clock manager refactor. [HOW?] Use num_memclk_level from num_entries_per_clk struct for getting the correct max mem speed. Reviewed-by: Jun Lei Acked-by: Brian Chang Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Avoid setting pixel rate divider to N/A

2022-12-14T10:40:49+00:00

[ Upstream commit 2a5dd86a69ea5435f1a837bdb7fafcda609a7c91 ] [Why] Pixel rate divider values should never be set to N/A (0xF) as the K1/K2 field is only 1/2 bits wide. [How] Set valid divider values for virtual and FRL/DP2 cases. Reviewed-by: Nicholas Kazlauskas Acked-by: Brian Chang Signed-off-by: Taimur Hassan Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Use viewport height for subvp mall allocation size

2022-12-14T10:40:49+00:00

[ Upstream commit dd2c028c1395d622df7ddd6837f8ab2dc94008ee ] [WHY?] MALL allocation size depends on the viewport height, not the addressable vertical lines, which will not match when scaling. [HOW?] Base MALL allocation size calculations off viewport height. Reviewed-by: Alvin Lee Reviewed-by: Martin Leung Acked-by: Brian Chang Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Update soc bounding box for dcn32/dcn321

2022-12-02T16:43:18+00:00

commit 5d82c82f1dbee264f7a94587adbbfee607706902 upstream. [Description] New values for soc bounding box and dummy pstate. Reviewed-by: Jun Lei Acked-by: Brian Chang Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.0.x Signed-off-by: Greg Kroah-Hartman

drm/amd/dc/dce120: Fix audio register mapping, stop triggering KASAN

2022-12-02T16:43:17+00:00

commit 44035ec2fde1114254ee465f9ba3bb246b0b6283 upstream. There's been a very long running bug that seems to have been neglected for a while, where amdgpu consistently triggers a KASAN error at start: BUG: KASAN: global-out-of-bounds in read_indirect_azalia_reg+0x1d4/0x2a0 [amdgpu] Read of size 4 at addr ffffffffc2274b28 by task modprobe/1889 After digging through amd's rather creative method for accessing registers, I eventually discovered the problem likely has to do with the fact that on my dce120 GPU there are supposedly 7 sets of audio registers. But we only define a register mapping for 6 sets. So, fix this and fix the KASAN warning finally. Signed-off-by: Lyude Paul Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/display: use uclk pstate latency for fw assisted mclk validation dcn32

2022-12-02T16:43:15+00:00

[ Upstream commit c149947b188c651b943c1d8ca1494d1a98a3e27f ] [WHY?] DCN32 uses fclk pstate watermarks for dummy pstate, and must always be supported. [HOW?] Validation needs to be run with fclk pstate latency set as the dummy pstate latency to get correct prefetch and bandwidth outputs. Reviewed-by: Jun Lei Acked-by: Tom Chung Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fix calculation for cursor CAB allocation

2022-12-02T16:43:11+00:00

[ Upstream commit 4d285241230676ba8b888701b89684b4e0360fcc ] [Why] The cursor size (in memory) is currently incorrectly calculated, resulting not enough CAB being allocated for static screen cursor in MALL refresh. This results in cursor image corruption. [How] Use cursor pitch instead of cursor width when calculating cursor size. Update num cache lines calculation to use the result of the cursor size calculation instead of manually recalculating again. Reviewed-by: Alvin Lee Acked-by: Tom Chung Signed-off-by: George Shen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.0.x Signed-off-by: Sasha Levin

drm/amd/display: Update MALL SS NumWays calculation

2022-12-02T16:43:11+00:00

[ Upstream commit 525a65c77db51cf5d6c6d8e3f8d07efeb2270416 ] [Description] Update MALL SS NumWays calculation according to programming guide. Reviewed-by: Jun Lei Acked-by: Jasdeep Dhillon Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Stable-dep-of: 4d2852412306 ("drm/amd/display: Fix calculation for cursor CAB allocation") Signed-off-by: Sasha Levin

drm/amd/display: Add debug option for allocating extra way for cursor

2022-12-02T16:43:11+00:00

[ Upstream commit 6eef37460584269b240f45aa47ebb61aae848082 ] [Why and How] - Add a debug option for allocating extra way for cursor - Remove usage of cache_cursor_addr since it's not gaurenteed to be populated - Include cursor size in MALL calculation if it exceeds the DCN cursor buffer size (and don't need extra way for cursor) Reviewed-by: Aurabindo Pillai Acked-by: Wayne Lin Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Stable-dep-of: 4d2852412306 ("drm/amd/display: Fix calculation for cursor CAB allocation") Signed-off-by: Sasha Levin