kernel/linux.git/drivers/gpu/drm/amd/display/dc/resource, branch linux-6.9.y

drm/amd/display: Add NULL pointer check for kzalloc

2024-07-11T10:50:59+00:00

[ Upstream commit 8e65a1b7118acf6af96449e1e66b7adbc9396912 ] [Why & How] Check return pointer of kzalloc before using it. Reviewed-by: Alex Hung Acked-by: Wayne Lin Signed-off-by: Hersen Wu Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: correct hostvm flag

2024-07-05T07:37:58+00:00

[ Upstream commit 3a13d1fddaf51b98cdba20b486cb8fd6080b71b7 ] [Why] Hostvm should be enabled/disabled accordding to the status of riommu_active, but hostvm always be disabled on DCN31 which causes underflow [How] Set correct hostvm flag on DCN31 Acked-by: Wayne Lin Signed-off-by: Sherry Wang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Ensure that dmcub support flag is set for DCN20

2024-05-01T01:30:16+00:00

In the DCN20 resource initialization, ensure that DMCUB support starts configured as true. Signed-off-by: Rodrigo Siqueira Acked-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Update dcn351 to latest dcn35 config

2024-03-27T12:57:39+00:00

[why & how] There were some fixes in dcn35 that need to be ported over to dcn351 to prevent any regression. Signed-off-by: Sung Joon Kim Reviewed-by: Liu, Xi (Alex) Signed-off-by: Alex Deucher

drm/amd/display: Init DPPCLK from SMU on dcn32

2024-03-20T17:12:58+00:00

[WHY & HOW] DPPCLK ranges should be obtained from the SMU when available. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Chaitanya Dhere Acked-by: Alex Hung Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Override min required DCFCLK in dml1_validate

2024-03-20T17:12:58+00:00

[WHY]: Increasing min DCFCLK addresses underflow issues that occur when phantom pipe is turned on for some Sub-Viewport configs [HOW]: dcn32_override_min_req_dcfclk is added to override DCFCLK value in dml1_validate when subviewport is being used. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Alvin Lee Acked-by: Alex Hung Signed-off-by: Sohaib Nadeem Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: add DC changes for DCN351

2024-03-04T20:59:08+00:00

Add DC support for DCN 3.5.1. Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Drop unnecessary header

2024-02-22T15:26:08+00:00

A long time ago, the slab header was added to multiple files in DC. We also included it in the os_types.h, which is included in many of those DC files. At this point, there is no need to insert the slab.h header in multiple files, so this commit drops those includes. Tested-by: Daniel Wheeler Reviewed-by: Hamza Mahfooz Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: reenable windowed mpo odm support on dcn32 and dcn321

2024-02-22T15:25:36+00:00

[why] The feature was disabled due to regression found during testing. Now that all the pending issues are addressed, we are reenabling the power saving feature again. The feature optimizes dispclk level when user is using MPO capable broswers or watching MPO capable videos in windowed mode. The feature achieves power optimization by utilizing free pipes to process incoming pixels in parallel. So it reduces max dispclk requirements for each pipe. Previously ODM power optimization will be disabled when MPO plane is present due to technical challeges. This is mainly because ODM divides pixel workload with respect to stream but MPO plane position and size are arbitrary with respect to stream. The pixel processing workload of an MPO plane is not guarenteed to be evenly distributed across DCN pipes. For example if a plane is moved inside single ODM slice, all the processing for the plane is distributed to the pipe in the current ODM slice, while the other ODM slices don't need to process this plane. If the plane is then moved to the middle crosing two ODM slices, each ODM slice gets half of the workload. This is especially difficult when the plane itself has a large source rect which can't be processed by single DCN pipe. In this case we can't enable ODM power optimization when the plane is only within one ODM slice. [how] To overcome the challeges, new pipe resource management is in place to make sure a plane is validated with ODM power optimization support if it can be validated regardless of its position and the same pipe topology can be used regardless of the plane's position. When the plane is moved outside current ODM slice, we will set recout to 0 so the pipe can be idling without the need to update pipe topology. When the user resizes a plane, it may result in downscaling ratio changes. When the downscaling ratio is above single pipe's threshold, we will seamlessly exit ODM power optimization and applies MPC combine to support the plane. when downscaling ratio becomes smaller, we will seamlessly enter ODM power optimization again. All these pipe transitions happen automatically and quietly when the conditions are met without any visual impacts to the user. Reviewed-by: Martin Leung Acked-by: Rodrigo Siqueira Tested-by: Daniel Wheeler Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher

drm/amd/display: Increase ips2_eval delay for DCN35

2024-02-14T22:15:15+00:00

[Why] New worst-case measurement observed at 1897us. [How] Increase to 2000us to cover the new worst case + margin. Reviewed-by: Ovidiu Bunea Acked-by: Aurabindo Pillai Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher