<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/optc, branch v6.18.22</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.18.22</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.18.22'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2025-08-27T17:57:50+00:00</updated>
<entry>
<title>drm/amd/display: wait for otg update pending latch before clock optimization</title>
<updated>2025-08-27T17:57:50+00:00</updated>
<author>
<name>Yihan Zhu</name>
<email>Yihan.Zhu@amd.com</email>
</author>
<published>2025-08-13T20:05:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f382e2d0faad0e0d73f626dbd71f2a4fce03975b'/>
<id>urn:sha1:f382e2d0faad0e0d73f626dbd71f2a4fce03975b</id>
<content type='text'>
[WHY &amp; HOW]
OTG pending update unlatched will cause system fail, wait OTG fully disabled to
avoid this error.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Yihan Zhu &lt;Yihan.Zhu@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Wait until OTG enable state is cleared</title>
<updated>2025-08-11T15:13:21+00:00</updated>
<author>
<name>TungYu Lu</name>
<email>tungyu.lu@amd.com</email>
</author>
<published>2025-07-15T08:56:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e7496c15d830689cc4fc666b976c845ed2c5ed28'/>
<id>urn:sha1:e7496c15d830689cc4fc666b976c845ed2c5ed28</id>
<content type='text'>
[Why]
Customer reported an issue that OS starts and stops device multiple times
during driver installation. Frequently disabling and enabling OTG may
prevent OTG from being safely disabled and cause incorrect configuration
upon the next enablement.

[How]
Add a wait until OTG_CURRENT_MASTER_EN_STATE is cleared as a short term
solution.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: TungYu Lu &lt;tungyu.lu@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Constify struct timing_generator_funcs</title>
<updated>2025-05-29T14:57:31+00:00</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2025-05-24T16:51:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=347efe5b396c61bc129832910665d899ee86448e'/>
<id>urn:sha1:347efe5b396c61bc129832910665d899ee86448e</id>
<content type='text'>
'struct timing_generator_funcs' are not modified in these drivers.

Constifying these structures moves some data to a read-only section, so
increases overall security, especially when the structure holds some
function pointers.

Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: wait for updates to latch before locking</title>
<updated>2025-04-07T22:01:08+00:00</updated>
<author>
<name>Ausef Yousof</name>
<email>Ausef.Yousof@amd.com</email>
</author>
<published>2025-03-28T15:06:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=556db637c27a463cd6bafa40714ea1245414456a'/>
<id>urn:sha1:556db637c27a463cd6bafa40714ea1245414456a</id>
<content type='text'>
[why&amp;how]
It is possible for an update to acquire otg lock and begin programming
while the previous update has not completed and its values have not
latched. The correct way to go about this is to wait until the vupdate
pulses so we can be sure that previous updates have latched and we can
continue with the current update pipe programming, otherwise during
consecutive full updates we will have corruption flash on the screen.

The corruption flash occurs specifically on configs that require odm
combine, and its local to a specific pipe (will not flash across whole
screen). This ticket is across the otg slave, but it may also appear
across master.

Reviewed-by: Leo Chen &lt;leo.chen@amd.com&gt;
Signed-off-by: Ausef Yousof &lt;Ausef.Yousof@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactor DCN4x and related code</title>
<updated>2025-02-25T16:44:02+00:00</updated>
<author>
<name>Patel, Swapnil</name>
<email>Swapnil.Patel@amd.com</email>
</author>
<published>2025-02-09T16:42:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=02a2793ab27e3aa3f345f4e7761005e5c9e3ebd4'/>
<id>urn:sha1:02a2793ab27e3aa3f345f4e7761005e5c9e3ebd4</id>
<content type='text'>
[why &amp; how]
Refactor existing code related to DCN4x for better code sharing with
other modules.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Swapnil Patel &lt;Swapnil.Patel@amd.com&gt;
Signed-off-by: Zaeem Mohamed &lt;zaeem.mohamed@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Allow reuse of of DCN4x code</title>
<updated>2025-02-13T02:03:01+00:00</updated>
<author>
<name>Dmytro</name>
<email>dmytro.laktyushkin@amd.com</email>
</author>
<published>2024-10-25T14:31:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2739bd123782f9bedc39285b3965ff2b4b3e6411'/>
<id>urn:sha1:2739bd123782f9bedc39285b3965ff2b4b3e6411</id>
<content type='text'>
Remove the static qualifier to make it available for code sharing
with other components.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Dmytro &lt;dmytro.laktyushkin@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: log destination of vertical interrupt</title>
<updated>2025-02-13T02:02:57+00:00</updated>
<author>
<name>Josip Pavic</name>
<email>Josip.Pavic@amd.com</email>
</author>
<published>2025-01-07T16:00:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=06b0a4ad7162b9dd7e52dbec320ea9d080d9e551'/>
<id>urn:sha1:06b0a4ad7162b9dd7e52dbec320ea9d080d9e551</id>
<content type='text'>
[Why]
Knowing the destination of OTG's vertical interrupt 2 is useful for
debugging, but it is not currently included in the OTG state readback
logic

[How]
Read the OTG interrupt destination register to get the vertical interrupt
2 destination on ASICs that have this register when reading back the OTG
state from hardware

Reviewed-by: Sung Lee &lt;sung.lee@amd.com&gt;
Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Josip Pavic &lt;Josip.Pavic@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add support to configure CRC window on specific CRC instance</title>
<updated>2025-01-10T17:03:45+00:00</updated>
<author>
<name>Wayne Lin</name>
<email>Wayne.Lin@amd.com</email>
</author>
<published>2024-12-06T05:51:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b6fcc3867d746c181d253b110236985b9b2ee2aa'/>
<id>urn:sha1:b6fcc3867d746c181d253b110236985b9b2ee2aa</id>
<content type='text'>
[Why]
Have the need to specify the CRC window on specific CRC engine.
dc_stream_configure_crc() today calculates CRC on crc engine 0 only and always
resets CRC engine at first.

[How]
Add index parameter to dc_stream_configure_crc() for selecting the desired crc
engine. Additionally, add another parameter to specify whether to skip the
default reset of crc engine.

Reviewed-by: HaoPing Liu &lt;haoping.liu@amd.com&gt;
Signed-off-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: DML2.1 Post-Si Cleanup</title>
<updated>2025-01-10T17:00:34+00:00</updated>
<author>
<name>Rafal Ostrowski</name>
<email>rostrows@amd.com</email>
</author>
<published>2024-12-17T14:50:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=63ab80d9ac0adae2066b140ec30481ba4648140d'/>
<id>urn:sha1:63ab80d9ac0adae2066b140ec30481ba4648140d</id>
<content type='text'>
[Why]
There are a few cleanup and refactoring tasks that need to be done
with the DML2.1 wrapper and DC interface to remove dependencies on
legacy structures and N-1 prototypes.

[How]
Implemented pipe_ctx-&gt;global_sync.
Implemented new functions to use pipe_ctx-&gt;hubp_regs and
pipe_ctx-&gt;global_sync:
- hubp_setup2
- hubp_setup_interdependent2
- Several other new functions for DCN 4.01 to support newer structures

Removed dml21_update_pipe_ctx_dchub_regs
Removed dml21_extract_legacy_watermark_set
Removed dml21_populate_pipe_ctx_dlg_param
Removed outdated dcn references in DML2.1 wrapper.

Reviewed-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Rafal Ostrowski &lt;rostrows@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Extend dc_stream_get_crc to support 2nd crc engine</title>
<updated>2025-01-06T19:44:26+00:00</updated>
<author>
<name>Wayne Lin</name>
<email>Wayne.Lin@amd.com</email>
</author>
<published>2024-07-23T07:01:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=10008a962b2d46e9672a89359d5740fa5c8fc9d7'/>
<id>urn:sha1:10008a962b2d46e9672a89359d5740fa5c8fc9d7</id>
<content type='text'>
[Why &amp; How]
Since now we can set multiple crc windows for secure display, add a new input
parameter for dc_stream_get_crc to indicate to fetch crc from which crc
engine.

Reviewed-by: HaoPing Liu &lt;haoping.liu@amd.com&gt;
Signed-off-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
