<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/link, branch v6.4</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.4</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.4'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-06-13T21:16:35+00:00</updated>
<entry>
<title>drm/amd/display: limit DPIA link rate to HBR3</title>
<updated>2023-06-13T21:16:35+00:00</updated>
<author>
<name>Peichen Huang</name>
<email>peichen.huang@amd.com</email>
</author>
<published>2023-05-31T05:36:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7c5835bcb9176df94683396f1c0e5df6bf5094b3'/>
<id>urn:sha1:7c5835bcb9176df94683396f1c0e5df6bf5094b3</id>
<content type='text'>
[Why]
DPIA doesn't support UHBR, driver should not enable UHBR
for dp tunneling

[How]
limit DPIA link rate to HBR3

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Signed-off-by: Peichen Huang &lt;peichen.huang@amd.com&gt;
Reviewed-by: Mustapha Ghaddar &lt;Mustapha.Ghaddar@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: enable dpia validate</title>
<updated>2023-05-18T13:58:35+00:00</updated>
<author>
<name>Mustapha Ghaddar</name>
<email>mghaddar@amd.com</email>
</author>
<published>2023-04-28T16:13:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6d600229df1ed06f46ba68ac706d9f44ba8c5fb4'/>
<id>urn:sha1:6d600229df1ed06f46ba68ac706d9f44ba8c5fb4</id>
<content type='text'>
Use dpia_validate_usb4_bw() function

Fixes: a8b537605e22 ("drm/amd/display: Add function pointer for validate bw usb4")
Reviewed-by: Roman Li &lt;roman.li@amd.com&gt;
Reviewed-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Mustapha Ghaddar &lt;mghaddar@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Improvement for handling edp link training fails</title>
<updated>2023-04-27T02:35:02+00:00</updated>
<author>
<name>Jingwen Zhu</name>
<email>Jingwen.Zhu@amd.com</email>
</author>
<published>2023-03-30T08:38:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e0cce122514ff76c3c986103c94de68fbb401949'/>
<id>urn:sha1:e0cce122514ff76c3c986103c94de68fbb401949</id>
<content type='text'>
[Why]
The eDP retrain will cause the DPCD 300 to be reset to default.
And cause the brightness can't be set correctly.

[How]
delete the call to edp panel power control in both
enable_link_output/disable_link_output entirely and
only call edp panel control in enable_link_dp and 
disable_link_dp once.

Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Jingwen Zhu &lt;Jingwen.Zhu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Apply correct panel mode when reinitializing hardware</title>
<updated>2023-04-27T02:34:29+00:00</updated>
<author>
<name>Michael Mityushkin</name>
<email>michael.mityushkin@amd.com</email>
</author>
<published>2023-03-30T15:35:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=56d8ce9d8c17bea955b0c2551ee86149486890ae'/>
<id>urn:sha1:56d8ce9d8c17bea955b0c2551ee86149486890ae</id>
<content type='text'>
[Why]
When link training during engine recovery, ASSR might fail causing panel
mode to be reset to default. This should not happen for eDP as it
will prevent the panel from turning back on.

[How]
Added dp_panel_mode to struct dc_link to remember previously applied
panel mode. Do not reset panel mode to default while performing link
training if previously used panel mode = eDP.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Michael Mityushkin &lt;michael.mityushkin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add logging when DP link training Clock recovery is Successful</title>
<updated>2023-04-14T17:47:49+00:00</updated>
<author>
<name>Srinivasan Shanmugam</name>
<email>srinivasan.shanmugam@amd.com</email>
</author>
<published>2023-04-13T19:50:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=88c7ad91e378775a08f54b4a85068d51b5cf52f3'/>
<id>urn:sha1:88c7ad91e378775a08f54b4a85068d51b5cf52f3</id>
<content type='text'>
Log when Clock recovery is successful, as part of
DP link training process.

Cc: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Cc: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Signed-off-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Reviewed-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add logging when setting DP sink power state fails</title>
<updated>2023-04-14T17:47:49+00:00</updated>
<author>
<name>Srinivasan Shanmugam</name>
<email>srinivasan.shanmugam@amd.com</email>
</author>
<published>2023-04-13T15:49:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ca9beb8aac68468f1778ad0e0fdad4e204f91393'/>
<id>urn:sha1:ca9beb8aac68468f1778ad0e0fdad4e204f91393</id>
<content type='text'>
Log if we fail to setup sink power states.

Cc: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Cc: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Reviewed-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add logging for DP link traning Test Pattern Seqeunces</title>
<updated>2023-04-11T22:03:45+00:00</updated>
<author>
<name>Srinivasan Shanmugam</name>
<email>srinivasan.shanmugam@amd.com</email>
</author>
<published>2023-04-07T08:52:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3e3320a7d96c1a5c66b60fbabb38af1f4c4fae1a'/>
<id>urn:sha1:3e3320a7d96c1a5c66b60fbabb38af1f4c4fae1a</id>
<content type='text'>
Add some more logging for DP link traning test pattern seqeunces
for better debugging.

Cc: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Reviewed-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display : Log DP link training downspread info</title>
<updated>2023-04-11T22:03:45+00:00</updated>
<author>
<name>Srinivasan Shanmugam</name>
<email>srinivasan.shanmugam@amd.com</email>
</author>
<published>2023-04-09T17:05:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=aee89b7d0929bfc6530a1468d34e0befc1991389'/>
<id>urn:sha1:aee89b7d0929bfc6530a1468d34e0befc1991389</id>
<content type='text'>
Update the existing log with DP LT downspread info:

[Downstream devices shall support down spreading of the link clock.
The down-spread amplitude shall either be disabled (0.0%) or up to 0.5%,
as written by the upstream device to the DOWNSPREAD_CTRL register
(DPCD 00107h). The modulation frequency range shall be 30 to 33 kHz]

Besides, fix checkpatch warning:

CHECK: Alignment should match open parenthesis

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Reviewed-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Improve robustness of FIXED_VS link training at DP1 rates</title>
<updated>2023-04-11T22:03:43+00:00</updated>
<author>
<name>Michael Strauss</name>
<email>michael.strauss@amd.com</email>
</author>
<published>2023-03-24T14:48:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7727e7b60f82e8265a1061b81379f5a7bce0dba6'/>
<id>urn:sha1:7727e7b60f82e8265a1061b81379f5a7bce0dba6</id>
<content type='text'>
[WHY]
New sequence for transparent mode DP1.x link training was provided by LTTPR
vendor

[HOW]
Implement new FIXED_VS sequence, increase LT retry count to minimize
any potential intermittent lightup failures

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Michael Strauss &lt;michael.strauss@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: skip CLEAR_PAYLOAD_ID_TABLE if device mst_en is 0</title>
<updated>2023-03-31T15:18:54+00:00</updated>
<author>
<name>Peichen Huang</name>
<email>PeiChen.Huang@amd.com</email>
</author>
<published>2023-03-20T01:34:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a1c9a1e27022d13c70a14c4faeab6ce293ad043b'/>
<id>urn:sha1:a1c9a1e27022d13c70a14c4faeab6ce293ad043b</id>
<content type='text'>
[Why]
Some dock and mst monitor don't like to receive CLEAR_PAYLOAD_ID_TABLE
when mst_en is set to 0. It doesn't make sense to do so in source
side, either.

[How]
Don't send CLEAR_PAYLOAD_ID_TABLE if mst_en is 0

Reviewed-by: George Shen &lt;George.Shen@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Peichen Huang &lt;PeiChen.Huang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
