kernel/linux.git/drivers/gpu/drm/amd/display/dc/inc, branch v6.6.149

drm/amd/display: Increase block_sequence array size

2025-06-04T12:42:10+00:00

[ Upstream commit 3a7810c212bcf2f722671dadf4b23ff70a7d23ee ] [Why] It's possible to generate more than 50 steps in hwss_build_fast_sequence, for example with a 6-pipe asic where all pipes are in one MPC chain. This overflows the block_sequence buffer and corrupts block_sequence_steps, causing a crash. [How] Expand block_sequence to 100 items. A naive upper bound on the possible number of steps for a 6-pipe asic, ignoring the potential for steps to be mutually exclusive, is 91 with current code, therefore 100 is sufficient. Reviewed-by: Alvin Lee Signed-off-by: Joshua Aberback Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Pass pwrseq inst for backlight and ABM

2024-01-20T10:51:48+00:00

commit b17ef04bf3a4346d66404454d6a646343ddc9749 upstream. [Why] OTG inst and pwrseq inst mapping is not align therefore we cannot use otg_inst as pwrseq inst to get DCIO register. [How] 1. Pass the correct pwrseq instance to dmub when set abm pipe. 2. LVTMA control index change from panel_inst to pwrseq_inst. Tested-by: Daniel Wheeler Reviewed-by: Phil Hsieh Acked-by: Rodrigo Siqueira Signed-off-by: Lewis Huang Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/display: Refactor edp power control

2023-12-08T07:52:24+00:00

[ Upstream commit 45f98fccb1f6895f527bd5f811f23478c2f920f5 ] [Why & How] To organize the edp power control a bit: 1. add flag in dc_link to indicate dc to skip all implicit eDP power control. 2. add edp_set_panel_power link service for DM to call. Reviewed-by: Aric Cyr Reviewed-by: Jun Lei Acked-by: Wayne Lin Signed-off-by: Ian Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Stable-dep-of: b0399e22ada0 ("drm/amd/display: Remove power sequencing check") Signed-off-by: Sasha Levin

drm/amd/display: add seamless pipe topology transition check

2023-11-28T17:19:39+00:00

[ Upstream commit 15c6798ae26d5c7a7776f4f7d0c1fa8c462688a2 ] [why] We have a few cases where we need to perform update topology update in dc update interface. However some of the updates are not seamless This could cause user noticible glitches. To enforce seamless transition we are adding a checking condition and error logging so the corruption as result of non seamless transition can be easily spotted. Reviewed-by: Dillon Varone Acked-by: Stylon Wang Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Blank phantom OTG before enabling

2023-11-28T17:19:39+00:00

[ Upstream commit e87a6c5b7780b5f423797351eb586ed96cc6d151 ] [Description] Before enabling the phantom OTG for an update we must enable DPG to avoid underflow. Reviewed-by: Samson Tam Acked-by: Stylon Wang Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Add DPIA Link Encoder Assignment Fix

2023-09-11T22:30:03+00:00

For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design. Reviewed-by: George Shen Acked-by: Hamza Mahfooz Signed-off-by: Mustapha Ghaddar Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amd/display: avoid crash and add z8_marks related in dml

2023-08-15T22:08:28+00:00

[why] add dml1 used calculate_wm_and_dlg function pointer check to prevent crash. add z8 watermarks to struct for later asic use Reviewed-by: Alvin Lee Acked-by: Stylon Wang Signed-off-by: Charlene Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: implement pipe type definition and adding accessors

2023-08-15T22:08:28+00:00

[why] There is a lack of encapsulation of pipe connection representation in pipe context. This has caused many challenging bugs and coding errors with repeated logic to identify the same pipe type. [how] Formally define pipe types and provide getters to identify a pipe type and find a pipe based on specific requirements. Update existing logic in non dcn specific files and dcn32 and future versions to use the new accessors. Reviewed-by: Jun Lei Acked-by: Stylon Wang Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Support Compliance Test Pattern Generation with DP2 Retimer

2023-08-15T22:08:27+00:00

[WHY] Certain retimer requires workarounds in order to correctly output test patterns. [HOW] Add vendor-specific aux sequences to program retimer's TX and pattern generator when specific compliance test patterns are requested by sink. Note: SQ128 w/a in DPMF mode only works in one flip orientation currently Reviewed-by: Hansen Dsouza Reviewed-by: Wenjing Liu Acked-by: Stylon Wang Signed-off-by: Michael Strauss Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: rename acquire_idle_pipe_for_layer to acquire_free_pipe_as_sec_dpp_pipe

2023-08-07T21:14:09+00:00

[why] Secondary DPP pipes are used for rendering secondary layers of planes. The name "for layer" doesn't make it obvious. The function is acquiring a free pipe as secondary dpp pipe only. We rename it so it is more obvious. In a future follow up change, we want to add functions to acquire free pipe as opp head pipe or otg master pipe as well. They will have their separate allocation priority. Reviewed-by: Jun Lei Acked-by: Tom Chung Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher