<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/inc, branch v5.10.263</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v5.10.263</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v5.10.263'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2025-04-10T12:30:52+00:00</updated>
<entry>
<title>drm/amd/display: fix odm scaling</title>
<updated>2025-04-10T12:30:52+00:00</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2021-05-10T14:19:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=71b1af48c858e2906a029aac178b85418660d697'/>
<id>urn:sha1:71b1af48c858e2906a029aac178b85418660d697</id>
<content type='text'>
[ Upstream commit 6566cae7aef30da8833f1fa0eb854baf33b96676 ]

There are two issues with scaling calculations, odm recout
calculation and matching viewport to actual recout.

This change fixes both issues. Odm recout calculation via
special casing and viewport matching issue by reworking
the viewport calcualtion to use scaling ratios and recout
to derrive the required offset and size.

Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Stable-dep-of: 374c9faac5a7 ("drm/amd/display: Fix null check for pipe_ctx-&gt;plane_state in resource_build_scaling_params")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove interface for periodic interrupt 1</title>
<updated>2022-10-26T11:25:50+00:00</updated>
<author>
<name>Aric Cyr</name>
<email>aric.cyr@amd.com</email>
</author>
<published>2022-09-09T22:07:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=166feb964fc8d9065eae8301b08e39a9fdbebcda'/>
<id>urn:sha1:166feb964fc8d9065eae8301b08e39a9fdbebcda</id>
<content type='text'>
[ Upstream commit 97d8d6f075bd8f988589be02b91f6fa644d0b0b8 ]

[why]
Only a single VLINE interrupt is available so interface should not
expose the second one which is used by DMU firmware.

[how]
Remove references to periodic_interrupt1 and VLINE1 from DC interfaces.

Reviewed-by: Jaehyun Chung &lt;jaehyun.chung@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Revert check for flip pending before locking pipes</title>
<updated>2020-09-29T20:09:05+00:00</updated>
<author>
<name>Aric Cyr</name>
<email>aric.cyr@amd.com</email>
</author>
<published>2020-09-25T14:54:53+00:00</published>
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<id>urn:sha1:cbd975d0b12fca62408157ecc07379da2da8e0a5</id>
<content type='text'>
Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Calc DLG from dummy p-state if full p-state unsupported</title>
<updated>2020-09-29T20:08:50+00:00</updated>
<author>
<name>Joshua Aberback</name>
<email>joshua.aberback@amd.com</email>
</author>
<published>2020-09-25T14:54:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8e02c26a58f37cb35e730e01eae14f943fba4cf4'/>
<id>urn:sha1:8e02c26a58f37cb35e730e01eae14f943fba4cf4</id>
<content type='text'>
[Why]
Currently, when full p-state changes are not supported, DLG parameters
are calculated for no p-state support at all. However, we are required
to always support dummy p-state changes, so we should instead calculate
DLG based on dummy p-state latency when full p-state is unsupported.
This behaviour already exists for DCN2.

[How]
 - move DLG calculation inside WM calculation
 - if p-state unsupported, do not recalculate for set A, instead copy from
set C, and perform DLG calculation with dummy p-state latency

Signed-off-by: Joshua Aberback &lt;joshua.aberback@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Check for flip pending before locking pipes.</title>
<updated>2020-09-22T16:28:56+00:00</updated>
<author>
<name>Taimur Hassan</name>
<email>syed.hassan@amd.com</email>
</author>
<published>2020-09-10T14:13:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1'/>
<id>urn:sha1:99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1</id>
<content type='text'>
[Why]
When running a game/benchmark with v-sync disabled, disabling a plane
(which is v-sync) can cause an underflow. This is due to flips that are
pending before pipe locking being applied after locks are released and
pipes have been re-arranged or disconnected. This can potentially apply
a flip on the incorrect pipe.

[How]
Check that any pending flips are cleared before locking any pipes to
ensure flips are applied on the correct pipes.

Signed-off-by: Taimur Hassan &lt;syed.hassan@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: implement notify stream mask</title>
<updated>2020-09-15T21:52:41+00:00</updated>
<author>
<name>Eric Yang</name>
<email>Eric.Yang2@amd.com</email>
</author>
<published>2020-08-21T21:15:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0825d9658b5e6b9ec6220ac5d2500f683c9601e7'/>
<id>urn:sha1:0825d9658b5e6b9ec6220ac5d2500f683c9601e7</id>
<content type='text'>
[Why]
Send stream active state info to DMUB

[How]
Implement GPINT to notify stream mask

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: adding pathway to retrieve stutter period</title>
<updated>2020-09-15T21:52:41+00:00</updated>
<author>
<name>Martin Leung</name>
<email>martin.leung@amd.com</email>
</author>
<published>2020-08-28T14:48:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6b85151f6bcdb796dfdb4d2e07dbeb4340b6b173'/>
<id>urn:sha1:6b85151f6bcdb796dfdb4d2e07dbeb4340b6b173</id>
<content type='text'>
why:
some functions may need be dependent on stutter period in the future

how:
Extract from stutter calculations and place into perf_params structure

Signed-off-by: Martin Leung &lt;martin.leung@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Rename set_mst_bandwidth to align with DP spec</title>
<updated>2020-09-15T21:52:41+00:00</updated>
<author>
<name>George Shen</name>
<email>george.shen@amd.com</email>
</author>
<published>2020-08-18T22:42:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6c95320d01dcac321e9e89903a26a840838a0ef6'/>
<id>urn:sha1:6c95320d01dcac321e9e89903a26a840838a0ef6</id>
<content type='text'>
[Why]
The function set_mst_bandwidth is poorly name since it isn't clear what
it does, and it also does not reflect any part of the allocation sequence
described in the DP spec.

[How]
Rename the function set_mst_bandwidth to set_throttled_vcp_size.

Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Detect plane change when detect pipe change.</title>
<updated>2020-09-15T21:52:40+00:00</updated>
<author>
<name>JinZe.Xu</name>
<email>JinZe.Xu@amd.com</email>
</author>
<published>2020-08-13T08:59:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=498563cf9ca00dc4ee389cf2729dae81417a144f'/>
<id>urn:sha1:498563cf9ca00dc4ee389cf2729dae81417a144f</id>
<content type='text'>
[Why]
If plane has changed, dcn20_detect_pipe_changes doesn't update dc_plane_state-&gt;update_flags, and the following dcn20_program_pipe can't reprogram hubp correctly.

[How]
Add a new flags bit "plane_changed" in pipe_ctx-&gt;update_flags.If old plane isn’t identical to new plane, this bit will be set and guide “dcn20_program_pipe” to programing HUBP correctly.

Signed-off-by: JinZe.Xu &lt;JinZe.Xu@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Send DISPLAY_OFF after power down on boot</title>
<updated>2020-08-26T20:40:17+00:00</updated>
<author>
<name>Sung Lee</name>
<email>sung.lee@amd.com</email>
</author>
<published>2020-08-11T21:23:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=387f3a30cc895abcdad0791fa6c6f3c1f1a69c83'/>
<id>urn:sha1:387f3a30cc895abcdad0791fa6c6f3c1f1a69c83</id>
<content type='text'>
[WHY]
update_clocks might not be called on headless adapters. This means
DISPLAY_OFF may not be sent in headless cases.

[HOW]
If hardware is powered down on boot because it is headless (mode set
does not happen on that adapter) also send DISPLAY_OFF notification.

Signed-off-by: Sung Lee &lt;sung.lee@amd.com&gt;
Reviewed-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
