<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/inc, branch linux-4.20.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.20.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.20.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2018-10-09T22:02:15+00:00</updated>
<entry>
<title>drm/amd/display: clean up encoding checks</title>
<updated>2018-10-09T22:02:15+00:00</updated>
<author>
<name>Eric Yang</name>
<email>Eric.Yang2@amd.com</email>
</author>
<published>2018-09-14T19:55:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e15fc81f11854451ec8a8ed9168b8247e4e9a10b'/>
<id>urn:sha1:e15fc81f11854451ec8a8ed9168b8247e4e9a10b</id>
<content type='text'>
[Why]
All ASICS we support has YCbCr support, so
the check is unnecessary, the currently logic
in validate output also returns true all
the time, so the unneccessary logic is removed

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Calculate swizzle mode using bpp during validation</title>
<updated>2018-10-09T22:01:55+00:00</updated>
<author>
<name>Su Sung Chung</name>
<email>Su.Chung@amd.com</email>
</author>
<published>2018-09-13T19:26:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=74eac5f3b43eda8b518662b011d1f18d5560e144'/>
<id>urn:sha1:74eac5f3b43eda8b518662b011d1f18d5560e144</id>
<content type='text'>
[Why]
Previously bandwidth validation was failing because swizzle mode was not
initialized during plane_state allocation. The swizzle mode was
calculated using pixed format which is how swizzle mode is initially
calculated in addrlib.

[How]
* Set default swizzle mode for validation to DC_SW_UNKNOWN
* Created new function in dcn10_assign_swizzle_mode which sets the
  plane swizzle mode based on selected pixed format
* Added the call of assign_swizzle_mode into dc_validate_global_state
* Set failsafe swizzle mode back to DC_SW_LINEAR

Signed-off-by: Su Sung Chung &lt;Su.Chung@amd.com&gt;
Reviewed-by: Eric Yang &lt;eric.yang2@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: program v_update and v_ready with proper field</title>
<updated>2018-09-27T02:09:06+00:00</updated>
<author>
<name>Su Sung Chung</name>
<email>su.chung@amd.com</email>
</author>
<published>2018-09-07T20:51:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=fb2b1ea325b411262031435c951d189a75de94b9'/>
<id>urn:sha1:fb2b1ea325b411262031435c951d189a75de94b9</id>
<content type='text'>
[WHY]
There are two different variables used to calculate v_update and v_ready,
one for validation and the other for performance parameter calculation.
Before the variable for validation was used which caused underflow on
1080edp with vsr enabled

[HOW]
program v_update and v_ready with the variables for performance parameter
calculation

Signed-off-by: Su Sung Chung &lt;su.chung@amd.com&gt;
Reviewed-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Reorder resource_pool to put i2c with aux</title>
<updated>2018-09-11T03:43:39+00:00</updated>
<author>
<name>David Francis</name>
<email>David.Francis@amd.com</email>
</author>
<published>2018-08-09T14:05:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=43af9e040905ed71a77785b29d81889d87264bcb'/>
<id>urn:sha1:43af9e040905ed71a77785b29d81889d87264bcb</id>
<content type='text'>
[Why]
The i2c and aux engines are similar, and should be placed
next to eachother for readability

[How]
Reorder the elements of the resource_pool struct

Signed-off-by: David Francis &lt;David.Francis@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: num of sw i2c/aux engines less than num of connectors</title>
<updated>2018-09-11T03:43:18+00:00</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2018-08-21T13:35:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0e8e4fbf8d8905071c045f2922de55adbe1a6abe'/>
<id>urn:sha1:0e8e4fbf8d8905071c045f2922de55adbe1a6abe</id>
<content type='text'>
[why]
AMD Stoney reference board, there are only 2 pipes (not include
underlay), and 3 connectors. resource creation, only
2 I2C/AUX engines are created. Within dc_link_aux_transfer, when
pin_data_en =2, refer to enengines[ddc_pin-&gt;pin_data-&gt;en] = NULL.
NULL point is referred later causing system crash.

[how]
each asic design has fixed number of ddc engines at hw side.
for each ddc engine, create its i2x/aux engine at sw side.

Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: remove unused clk_src code</title>
<updated>2018-09-11T03:42:55+00:00</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2018-07-30T18:45:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e6ada54126cff629b422924e6497a13ce8bd890d'/>
<id>urn:sha1:e6ada54126cff629b422924e6497a13ce8bd890d</id>
<content type='text'>
Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Support reading hw state from debugfs file</title>
<updated>2018-08-27T20:20:49+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2018-08-15T16:00:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=46659a83e4662ed92000ec13445b8c0ca96fd2cc'/>
<id>urn:sha1:46659a83e4662ed92000ec13445b8c0ca96fd2cc</id>
<content type='text'>
[Why]

Logging hardware state can be done by triggering a write to the
debugfs file. It would also be useful to be able to read the hardware
state from the debugfs file to be able to generate a clean log without
timestamps.

[How]

Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log

Threading is an obvious concern when dealing with multiple debugfs
operations and blocking on global state in dm or dc seems unfavorable.

Adding an extra parameter for the debugfs log context state is the
implementation done here. Existing code that made use of DTN_INFO
and its associated macros needed to be refactored to support this.

We don't know the size of the log in advance so it reallocates the
log string dynamically. Once the log has been generated it's copied
into the user supplied buffer for the debugfs. This allows for seeking
support but it's worth nothing that unlike triggering output via
dmesg the hardware state might change in-between reads if your buffer
size is too small.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Jordan Lazare &lt;Jordan.Lazare@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: add support for LVDS (v5)</title>
<updated>2018-08-27T16:11:15+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-08-14T19:53:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=11c3ee48bd7c232c0a750b4dde8ee48f315dcdf3'/>
<id>urn:sha1:11c3ee48bd7c232c0a750b4dde8ee48f315dcdf3</id>
<content type='text'>
This adds support for LVDS displays.

v2: add support for spread spectrum, sink detect
v3: clean up enable_lvds_output
v4: fix up link_detect
v5: remove assert on 888 format

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=105880
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: implement DPMS DTN test v2</title>
<updated>2018-08-27T16:11:07+00:00</updated>
<author>
<name>Jun Lei</name>
<email>Jun.Lei@amd.com</email>
</author>
<published>2018-08-08T15:53:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=dd73043534515c1b8bf31f78f0e9945f5d95e0e6'/>
<id>urn:sha1:dd73043534515c1b8bf31f78f0e9945f5d95e0e6</id>
<content type='text'>
[why]
Existing DTN infrastructure in driver is hacky.  It uses implicit log
names, and also incorrect escape ID.

[how]
- Implement using generic DTN escape ID.
- Move file logging functionality from driver to to script; driver now outputs to string/buffer
- Move HWSS debug functionality to separate c file
- Add debug functionalty for per-block logging as CSV
- Add pretty print in python

Signed-off-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Create new i2c resource</title>
<updated>2018-08-27T16:11:05+00:00</updated>
<author>
<name>David Francis</name>
<email>David.Francis@amd.com</email>
</author>
<published>2018-07-23T18:12:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c85e6e546edd7e362693218a33a6f63217802fd3'/>
<id>urn:sha1:c85e6e546edd7e362693218a33a6f63217802fd3</id>
<content type='text'>
[Why]
I2C code did not match dc resource model and was generally
unpleasant

[How]
Move code into new svelte dce_i2c files, replacing various i2c
objects with two structs: dce_i2c_sw and dce_i2c_hw.  Fully split
sw and hw code paths.  Remove all redundant declarations.  Use
address lists to distinguish between versions.  Change dce80 code
to newer register access macros.

Signed-off-by: David Francis &lt;David.Francis@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
