kernel/linux.git/drivers/gpu/drm/amd/display/dc/inc/clock_source.h, branch v6.2

drm/amd/display: Use correct DTO_SRC_SEL for 128b/132b encoding

2022-07-25T21:16:45+00:00

[WHY] DP DTO isn't used for 128b/132b encoding [HOW] Check current link rate to determine whether using 8b/10b or 128/132b encoding Reviewed-by: Nicholas Kazlauskas Acked-by: Alex Hung Signed-off-by: Michael Strauss Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Synchronize displays with different timings

2021-02-22T23:05:48+00:00

[why] Vendor based fan noise improvement [how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y Signed-off-by: Vladimir Stempen Acked-by: Bindu Ramamurthy Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Keep clocks high before seamless boot done

2019-03-19T20:04:03+00:00

[Why] UEFI boot usually uses a boot profile that uses higher clocks and watermark settings. UEFI boot surface is less optimal, for example it uses linear surface [How] Before we finish our seamless boot sequence, keep the clock and watermark settings from boot. Update to optimal settings only after first flip away from UEFI frame buffer. Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: interface to check if timing can be seamless

2019-02-06T18:30:44+00:00

[Why] Need to figure out whether a timing we want to commit matches something that GOP already programmed, in which case we can decide to some optimizations [How] 1. Add way to check for DIG FE 2. Add way to check for matching OTG timing 3. Add way to check for matching pixel clock (if possible) - Currently only support DP for pixel clock, since it is easy to calc Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Use 100 Hz precision for pipe pixel clocks

2019-01-14T20:04:39+00:00

[Why] Users would like more accurate pixel clocks, especially for fractional "TV" frame rates like 59.94 Hz. [How] Store and communicate pixel clocks with 100 Hz accuracy from dc_crtc_timing through to BIOS command table setpixelclock call. Signed-off-by: Ken Chalmers Reviewed-by: Charlene Liu Acked-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: remove unused clk_src code

2018-09-11T03:42:55+00:00

Signed-off-by: Dmytro Laktyushkin Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: add display write back(DWB)

2017-09-26T22:16:36+00:00

Signed-off-by: Duke Du Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: HDMI YCbCr422 12bpc pixel format issue

2017-09-26T21:13:37+00:00

Signed-off-by: Charlene Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/dc: Add dc display driver (v2)

2017-09-26T21:01:32+00:00

Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher