<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/hwss, branch v6.7</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.7</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.7'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-12-19T20:20:57+00:00</updated>
<entry>
<title>drm/amd/display: disable FPO and SubVP for older DMUB versions on DCN32x</title>
<updated>2023-12-19T20:20:57+00:00</updated>
<author>
<name>Hamza Mahfooz</name>
<email>hamza.mahfooz@amd.com</email>
</author>
<published>2023-12-15T15:37:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3248211dd971ed2b614307eb42cecee3e6feecff'/>
<id>urn:sha1:3248211dd971ed2b614307eb42cecee3e6feecff</id>
<content type='text'>
There have recently been changes that break backwards compatibility,
that were introduced into DMUB firmware (for DCN32x) concerning FPO and
SubVP. So, since those are just power optimization features, we can just
disable them unless the user is using a new enough version of DMUB
firmware.

Cc: stable@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2870
Fixes: ed6e2782e974 ("drm/amd/display: For cursor P-State allow for SubVP")
Reported-by: Mikhail Gavrilov &lt;mikhail.v.gavrilov@gmail.com&gt;
Closes: https://lore.kernel.org/r/CABXGCsNRb0QbF2pKLJMDhVOKxyGD6-E+8p-4QO6FOWa6zp22_A@mail.gmail.com/
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix hw rotated modes when PSR-SU is enabled</title>
<updated>2023-12-11T17:41:05+00:00</updated>
<author>
<name>Hamza Mahfooz</name>
<email>hamza.mahfooz@amd.com</email>
</author>
<published>2023-12-05T19:55:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f528ee145bd0076cd0ed7e7b2d435893e6329e98'/>
<id>urn:sha1:f528ee145bd0076cd0ed7e7b2d435893e6329e98</id>
<content type='text'>
We currently don't support dirty rectangles on hardware rotated modes.
So, if a user is using hardware rotated modes with PSR-SU enabled,
use PSR-SU FFU for all rotated planes (including cursor planes).

Cc: stable@vger.kernel.org
Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support")
Reported-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2952
Tested-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Tested-by: Bin Li &lt;binli@gnome.org&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix MPCC 1DLUT programming</title>
<updated>2023-11-29T22:58:36+00:00</updated>
<author>
<name>Ilya Bakoulin</name>
<email>ilya.bakoulin@amd.com</email>
</author>
<published>2023-11-07T20:07:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6f395cebdd8927fbffdc3a55a14fcacf93634359'/>
<id>urn:sha1:6f395cebdd8927fbffdc3a55a14fcacf93634359</id>
<content type='text'>
[Why]
Wrong function is used to translate LUT values to HW format, leading to
visible artifacting in some cases.

[How]
Use the correct cm3_helper function.

Cc: stable@vger.kernel.org # 6.1+
Reviewed-by: Krunoslav Kovac &lt;krunoslav.kovac@amd.com&gt;
Acked-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Ilya Bakoulin &lt;ilya.bakoulin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: For cursor P-State allow for SubVP</title>
<updated>2023-11-07T17:03:30+00:00</updated>
<author>
<name>Alvin Lee</name>
<email>alvin.lee2@amd.com</email>
</author>
<published>2023-10-23T18:33:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ed6e2782e9747508888f671e1101250bb19045be'/>
<id>urn:sha1:ed6e2782e9747508888f671e1101250bb19045be</id>
<content type='text'>
[Description]
- Similar to FPO, SubVP should also force cursor P-State
  allow instead of relying on natural assertion
- Implement code path to force and unforce cursor P-State
  allow for SubVP

Reviewed-by: Samson Tam &lt;samson.tam@amd.com&gt;
Acked-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Signed-off-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable physymclk RCO</title>
<updated>2023-11-07T17:03:30+00:00</updated>
<author>
<name>Daniel Miess</name>
<email>daniel.miess@amd.com</email>
</author>
<published>2023-10-26T18:34:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e4c33fff2eae41d16d9760e56efc23dcc30c6b91'/>
<id>urn:sha1:e4c33fff2eae41d16d9760e56efc23dcc30c6b91</id>
<content type='text'>
[Why]
Enable the last of the RCO options for dcn35

[How]
Breakout RCO from dccg35_set_physymclk so that
physymclk RCO can be set in dccg_init without
disabling physymclk

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Jun Lei &lt;jun.lei@amd.com&gt;
Acked-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Signed-off-by: Daniel Miess &lt;daniel.miess@amd.com&gt;
Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix FRL assertion on boot</title>
<updated>2023-11-07T16:16:33+00:00</updated>
<author>
<name>Sung Joon Kim</name>
<email>sungkim@amd.com</email>
</author>
<published>2023-10-16T19:23:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f896cd2686817db915c265ff693a8dad7b6580dc'/>
<id>urn:sha1:f896cd2686817db915c265ff693a8dad7b6580dc</id>
<content type='text'>
[why]
Make sure to ungate the clocks on boot
so programming sequence is done successfully.

[how]
Move the ungate logic after bios init.

Reviewed-by: Xi (Alex) Liu &lt;xi.liu@amd.com&gt;
Acked-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Signed-off-by: Sung Joon Kim &lt;sungkim@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: On boot disable domain22 force power on</title>
<updated>2023-11-07T16:15:48+00:00</updated>
<author>
<name>Daniel Miess</name>
<email>daniel.miess@amd.com</email>
</author>
<published>2023-10-13T14:38:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=89830c62e677187a75b25202effbbf6611fc6552'/>
<id>urn:sha1:89830c62e677187a75b25202effbbf6611fc6552</id>
<content type='text'>
[Why]
HDCP2 enablement fails when domain22 is set to force
power on

[How]
Disable force power on for domain22 on startup

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Acked-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Signed-off-by: Daniel Miess &lt;daniel.miess@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix shaper using bad LUT params</title>
<updated>2023-10-26T23:02:06+00:00</updated>
<author>
<name>Ilya Bakoulin</name>
<email>ilya.bakoulin@amd.com</email>
</author>
<published>2023-10-06T19:57:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=85ca6e85303c10019710f31d4abedafab7994d68'/>
<id>urn:sha1:85ca6e85303c10019710f31d4abedafab7994d68</id>
<content type='text'>
[Why]
LUT params are not cleared after setting blend TF, which can lead to
same params being used for the shaper, if the shaper func is bypassed.

[How]
Set lut_params to NULL after program_1dlut.

Reviewed-by: Krunoslav Kovac &lt;krunoslav.kovac@amd.com&gt;
Acked-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Ilya Bakoulin &lt;ilya.bakoulin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Update FAMS sequence for DCN30 &amp; DCN32</title>
<updated>2023-10-26T23:00:23+00:00</updated>
<author>
<name>Alvin Lee</name>
<email>alvin.lee2@amd.com</email>
</author>
<published>2023-10-06T22:01:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f583db812bc9a97384303761932768e44d1d92a3'/>
<id>urn:sha1:f583db812bc9a97384303761932768e44d1d92a3</id>
<content type='text'>
Provide DCN32 specific sequence and update DCN30 sequence

Reviewed-by: Samson Tam &lt;samson.tam@amd.com&gt;
Acked-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix num_ways overflow error</title>
<updated>2023-10-26T23:00:15+00:00</updated>
<author>
<name>Samson Tam</name>
<email>samson.tam@amd.com</email>
</author>
<published>2023-10-05T05:31:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=79f3f1b66753b3a3a269d73676bf50987921f267'/>
<id>urn:sha1:79f3f1b66753b3a3a269d73676bf50987921f267</id>
<content type='text'>
[Why]
Helper function calculates num_ways using 32-bit.  But is
 returned as 8-bit.  If num_ways exceeds 8-bit, then it
 reports back the incorrect num_ways and erroneously
 uses MALL when it should not

[How]
Make returned value 32-bit and convert after it checks
 against caps.cache_num_ways, which is under 8-bit

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Acked-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Samson Tam &lt;samson.tam@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
