<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn32, branch v6.3</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-03-23T13:39:34+00:00</updated>
<entry>
<title>drm/amd/display: Set dcn32 caps.seamless_odm</title>
<updated>2023-03-23T13:39:34+00:00</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2023-03-09T20:58:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f9537b1fa7fb51c2162bc15ce469cbbf1ca0fbfe'/>
<id>urn:sha1:f9537b1fa7fb51c2162bc15ce469cbbf1ca0fbfe</id>
<content type='text'>
[Why &amp; How]
seamless_odm set was not picked up while
merging commit 2d017189e2b3 ("drm/amd/display:
Blank eDP on enable drv if odm enabled")

Fixes: 2d017189e2b3 ("drm/amd/display: Blank eDP on enable drv if odm enabled")
Reviewed-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix wrong index used in dccg32_set_dpstreamclk</title>
<updated>2023-03-23T13:39:34+00:00</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2023-03-09T21:14:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4c94e57c258cb7800aa5f3a9d9597d91291407a9'/>
<id>urn:sha1:4c94e57c258cb7800aa5f3a9d9597d91291407a9</id>
<content type='text'>
[Why &amp; How]
When merging commit 9af611f29034
("drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming"),
index change was not picked up.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Fixes: 9af611f29034 ("drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming")
Reviewed-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: disconnect MPCC only on OTG change</title>
<updated>2023-03-15T22:19:35+00:00</updated>
<author>
<name>Ayush Gupta</name>
<email>ayugupta@amd.com</email>
</author>
<published>2023-03-02T14:58:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7304ee979b6b6422f41a1312391a5e505fc29ccd'/>
<id>urn:sha1:7304ee979b6b6422f41a1312391a5e505fc29ccd</id>
<content type='text'>
[Why]
Framedrops are observed while playing Vp9 and Av1 10 bit
video on 8k resolution using VSR while playback controls
are disappeared/appeared

[How]
Now ODM 2 to 1 is disabled for 5k or greater resolutions on VSR.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Ayush Gupta &lt;ayugupta@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove OTG DIV register write for Virtual signals.</title>
<updated>2023-03-15T22:17:22+00:00</updated>
<author>
<name>Saaem Rizvi</name>
<email>SyedSaaem.Rizvi@amd.com</email>
</author>
<published>2023-02-27T23:55:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=709671ffb15dcd1b4f6afe2a9d8c67c7c4ead4a1'/>
<id>urn:sha1:709671ffb15dcd1b4f6afe2a9d8c67c7c4ead4a1</id>
<content type='text'>
[WHY]
Hot plugging and then hot unplugging leads to k1 and k2 values to
change, as signal is detected as a virtual signal on hot unplug. Writing
these values to OTG_PIXEL_RATE_DIV register might cause primary display
to blank (known hw bug).

[HOW]
No longer write k1 and k2 values to register if signal is virtual, we
have safe guards in place in the case that k1 and k2 is unassigned so
that an unknown value is not written to the register either.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Samson Tam &lt;Samson.Tam@amd.com&gt;
Reviewed-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Saaem Rizvi &lt;SyedSaaem.Rizvi@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add previously missing includes</title>
<updated>2023-02-16T03:24:39+00:00</updated>
<author>
<name>Arthur Grillo</name>
<email>arthurgrillo@riseup.net</email>
</author>
<published>2023-02-13T20:49:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8dc2507f4b24dc322da32dedab65d3d36979a79d'/>
<id>urn:sha1:8dc2507f4b24dc322da32dedab65d3d36979a79d</id>
<content type='text'>
Add includes that were previously missing to reduce the number of
-Wmissing-prototypes warnings.

Signed-off-by: Arthur Grillo &lt;arthurgrillo@riseup.net&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add function prototypes to headers</title>
<updated>2023-02-16T03:24:34+00:00</updated>
<author>
<name>Arthur Grillo</name>
<email>arthurgrillo@riseup.net</email>
</author>
<published>2023-02-13T20:49:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6884b0e4077676f21ebd310ac983d819ea109f89'/>
<id>urn:sha1:6884b0e4077676f21ebd310ac983d819ea109f89</id>
<content type='text'>
Add function prototypes to headers to reduce the number of
-Wmissing-prototypes warnings.

Signed-off-by: Arthur Grillo &lt;arthurgrillo@riseup.net&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix k1 k2 divider programming for phantom streams</title>
<updated>2023-02-14T21:00:18+00:00</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2023-01-30T18:07:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3b214bb7185d8284d7d4c53e15127f69a375abf6'/>
<id>urn:sha1:3b214bb7185d8284d7d4c53e15127f69a375abf6</id>
<content type='text'>
[Why &amp; How]
When k1 and k2 divider programming logic is executed for a phantom
stream, the corresponding master stream should be used for the
calculation. Fix the if condition to use the master stream for checking
signal type instead of the phantom stream.

Reviewed-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Set max vratio for prefetch to 7.9 for YUV420 MPO</title>
<updated>2023-02-14T20:47:26+00:00</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2023-01-25T17:33:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7cd07d9de8711a0d3f361c84d402e3d6b89ccede'/>
<id>urn:sha1:7cd07d9de8711a0d3f361c84d402e3d6b89ccede</id>
<content type='text'>
[Description]
- Single 4K60 playing YUV420 MPO video blocks P-State because
  the required VRatio for prefetch is too high (luma plane for
  YUV420 is 1bpe, so swath height is 16 and prefetch requires
  more lines)
- Allow max vratio per plane to be 7.9 for single display YUV420
  MPO video cases
- Ensure that global vratio prefetch (i.e. total prefetch BW vs.
  total active bandwidth) does not excited 4.0

Reviewed-by: Nevenko Stupar &lt;Nevenko.Stupar@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: break down dc_link.c</title>
<updated>2023-02-08T22:15:51+00:00</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2023-01-18T22:31:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=54618888d1ea7a26f8bccfb89e3c2420350c8047'/>
<id>urn:sha1:54618888d1ea7a26f8bccfb89e3c2420350c8047</id>
<content type='text'>
[why]
dc_link contains over 30k line of code, the decision is to break it
down to files residing in link folder based on functionality. This
change is the last break down change which will remove dc_link.c
file after everything is broken down.

[how]
Move remaining dc_link.c functions into link_detection, link_dpms,
link_validation, link_resource, and link_fpga and remove dc_link.

Reviewed-by: George Shen &lt;George.Shen@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Unassign does_plane_fit_in_mall function from dcn3.2</title>
<updated>2023-01-31T19:03:24+00:00</updated>
<author>
<name>George Shen</name>
<email>george.shen@amd.com</email>
</author>
<published>2023-01-19T22:09:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=cf76ce68c214b78bf151e84abaa0a2704fd38574'/>
<id>urn:sha1:cf76ce68c214b78bf151e84abaa0a2704fd38574</id>
<content type='text'>
[Why]
The hwss function does_plane_fit_in_mall not applicable to dcn3.2 asics.
Using it with dcn3.2 can result in undefined behaviour.

[How]
Assign the function pointer to NULL.

Reviewed-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
