kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn32, branch v6.2.2

drm/amd/display: Unassign does_plane_fit_in_mall function from dcn3.2

2023-02-02T03:45:50+00:00

[Why] The hwss function does_plane_fit_in_mall not applicable to dcn3.2 asics. Using it with dcn3.2 can result in undefined behaviour. [How] Assign the function pointer to NULL. Reviewed-by: Alvin Lee Acked-by: Alex Hung Signed-off-by: George Shen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix spelling mistake: "dram_clk_chanage" -> "dram_clk_change"

2022-12-09T21:50:30+00:00

There is a spelling mistake in the struct field dram_clk_chanage. Fix it. Signed-off-by: Colin Ian King Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Disable uclk pstate for subvp pipes

2022-12-06T15:16:11+00:00

[Description] When subvp is in use, main pipes should block unintended natural uclk pstate changes to prevent disruption to the state machine. Reviewed-by: Alvin Lee Acked-by: Stylon Wang Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programming

2022-11-29T16:03:38+00:00

[Description] - When transitioning FRL / DP2 is not required, we will always request DTBCLK = 0Mhz, but PMFW returns the min freq - This causes us to make DTBCLK requests every time we call optimize after transitioning from FRL to non-FRL - If DTBCLK is not required, request the min instead (then we only need to make 1 extra request at boot time) - Also when programming PIPE_DTO_SRC_SEL, don't programming for DP first, just programming once for the required selection (programming DP on an HDMI connection then switching back causes corruption) Reviewed-by: Dillon Varone Acked-by: Jasdeep Dhillon Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher

drm/amd/display: Use DCC meta pitch for MALL allocation requirements

2022-11-29T16:03:38+00:00

[Description] Calculations for determining DCC meta size should be pitch*height*bpp/256. Reviewed-by: Alvin Lee Acked-by: Jasdeep Dhillon Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher

drm/amd/display: Fix arithmetic error in MALL size calculations for subvp

2022-11-29T16:03:38+00:00

[Description] Need to subtract unused section of the viewport when calculating required space in MALL for subvp instead of adding, to prevent over allocation. Reviewed-by: Alvin Lee Acked-by: Jasdeep Dhillon Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher

drm/amd/display: Retain phantom pipes when min transition into subvp (#7358)

2022-11-29T16:03:38+00:00

[Description] - When entering into a SubVP config that requires a minimal transition we need to retain phantom pipes and also restore the mall config - This is because the min transition will remove phantom pipes from the context (shallow copy) and not restore it's original state - This is just a workaround, and needs a proper fix Reviewed-by: Jun Lei Acked-by: Jasdeep Dhillon Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher

drm/amd/display: Don't overwrite subvp pipe info in fast updates

2022-11-29T16:03:38+00:00

[Description] - This is a workaround to avoid concurrency issues -- a fast update creates a shallow copy of the dc current_state, and removes all subvp/phantom related flags. - We want to prevent the fast update thread from removing those flags in case there's another thread running that requires the info for proper programming Reviewed-by: Jun Lei Acked-by: Jasdeep Dhillon Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher

drm/amd/display: MALL SS calculations should iterate over all pipes for cursor

2022-11-29T16:03:38+00:00

[Description] MALL SS allocation calculations should iterate over all pipes to determine the the allocation size required for HW cursor. Reviewed-by: Alvin Lee Acked-by: Jasdeep Dhillon Signed-off-by: Dillon Varone Signed-off-by: Alex Deucher

drm/amd/display: Avoid setting pixel rate divider to N/A

2022-11-23T14:47:14+00:00

[Why] Pixel rate divider values should never be set to N/A (0xF) as the K1/K2 field is only 1/2 bits wide. [How] Set valid divider values for virtual and FRL/DP2 cases. Reviewed-by: Nicholas Kazlauskas Acked-by: Brian Chang Signed-off-by: Taimur Hassan Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher