<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn321, branch v6.3.2</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3.2</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3.2'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-01-31T19:00:57+00:00</updated>
<entry>
<title>drm/amd/display: fix MALL size hardcoded for DCN321</title>
<updated>2023-01-31T19:00:57+00:00</updated>
<author>
<name>Samson Tam</name>
<email>Samson.Tam@amd.com</email>
</author>
<published>2023-01-17T08:47:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=918d5166439078364453f2eb5b4d8e75095a510e'/>
<id>urn:sha1:918d5166439078364453f2eb5b4d8e75095a510e</id>
<content type='text'>
[Why]
MALL size available can vary for different SKUs
MALL size was still hardcoded for DCN321

[How]
Remove hardcoding MALL size for DCN321

Reviewed-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Samson Tam &lt;Samson.Tam@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: merge dc_link_dp into dc_link</title>
<updated>2023-01-24T18:26:25+00:00</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2023-01-09T21:52:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6ca7415f11af5200ab10bd420b513f846e9bfb99'/>
<id>urn:sha1:6ca7415f11af5200ab10bd420b513f846e9bfb99</id>
<content type='text'>
[why]
Temporarly merge dc_link_dp functions into dc_link for the
purpose of removing dc_link_dp files. This is a transitional
change for later commits where we will further refactor dc_link
file.

Reviewed-by: George Shen &lt;George.Shen@amd.com&gt;
Acked-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: adjust MALL size available for DCN32 and DCN321</title>
<updated>2023-01-24T18:26:25+00:00</updated>
<author>
<name>Samson Tam</name>
<email>Samson.Tam@amd.com</email>
</author>
<published>2023-01-11T18:31:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=235fef6c7fd341026eee90cc546e6e8ff8b2c315'/>
<id>urn:sha1:235fef6c7fd341026eee90cc546e6e8ff8b2c315</id>
<content type='text'>
[Why]
MALL size available can vary for different SKUs.
Use num_chans read from VBIOS to determine the available MALL size we can use

[How]
Define max_chans for DCN32 and DCN321.
If num_chans is max_chans, then return max_chans as we can access the
 entire MALL space.
Otherwise, define avail_chans as the number of available channels we are
 allowed instead.
Return corresponding number of channels back and use this to calculate
 available MALL size.

Reviewed-by: Nevenko Stupar &lt;Nevenko.Stupar@amd.com&gt;
Acked-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Signed-off-by: Samson Tam &lt;Samson.Tam@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: refactor ddc logic from dc_link_ddc to link_ddc</title>
<updated>2023-01-13T19:57:40+00:00</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2022-12-12T18:52:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a98cdd8c485600a2cfc15508a38c13c49b551fb1'/>
<id>urn:sha1:a98cdd8c485600a2cfc15508a38c13c49b551fb1</id>
<content type='text'>
[why]
1. Move dd_link_ddc functions to link_ddc.
2. Move link ddc functions declaration exposed in dc to link.h
3. Move link ddc functions declaration exposed in dm to dc_link.h
4. Remove i2caux_interface.h file

Tested-by: Daniel Wheeler &lt;Daniel.Wheeler@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add debug bit to disable unbounded requesting</title>
<updated>2022-12-15T17:18:18+00:00</updated>
<author>
<name>Dillon Varone</name>
<email>Dillon.Varone@amd.com</email>
</author>
<published>2022-11-26T07:03:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d7368ea9708b79c2e8fef95ee5bc8088a4b9c2f2'/>
<id>urn:sha1:d7368ea9708b79c2e8fef95ee5bc8088a4b9c2f2</id>
<content type='text'>
[Description]
Add debug bit to disable unbounded requesting.

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Dillon Varone &lt;Dillon.Varone@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove DTB DTO on CLK update</title>
<updated>2022-12-06T15:13:19+00:00</updated>
<author>
<name>Chris Park</name>
<email>Chris.Park@amd.com</email>
</author>
<published>2022-05-05T05:55:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c6ac25f646b6ce5edf0a719a314e3f31c7a99bb0'/>
<id>urn:sha1:c6ac25f646b6ce5edf0a719a314e3f31c7a99bb0</id>
<content type='text'>
[Why]
DTB DTO is programmed more correctly during
link enable.  Programming them on CLK update
which may arrive frequently and sporadically
per flip throws off DTB DTO.

[How]
Remove DTB DTO programming on clock update.

Reviewed-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Chris Park &lt;Chris.Park@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Retain phantom pipes when min transition into subvp (#7358)</title>
<updated>2022-11-29T16:03:38+00:00</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2022-11-17T16:55:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=aaae52110a381033d960c087bd276e2a857eb7cb'/>
<id>urn:sha1:aaae52110a381033d960c087bd276e2a857eb7cb</id>
<content type='text'>
[Description]
- When entering into a SubVP config that requires a minimal
  transition we need to retain phantom pipes and also restore
  the mall config
- This is because the min transition will remove phantom pipes
  from the context (shallow copy) and not restore it's original
  state
- This is just a workaround, and needs a proper fix

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Retain phantom plane/stream if validation fails</title>
<updated>2022-11-23T14:47:14+00:00</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2022-11-11T17:14:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9b216b7e38f5381bcc3ad21c5ac614aa577ab8f2'/>
<id>urn:sha1:9b216b7e38f5381bcc3ad21c5ac614aa577ab8f2</id>
<content type='text'>
[Description]
- If we fail validation, we should retain the phantom
  stream/planes
- Full updates assume that phantom pipes will be fully
  removed, but if validation fails we keep the phantom
  pipes
- Therefore we have to retain the plane/stream if validation
  fails (since the refcount is decremented before validation,
  and the expectation is that it's fully freed when the  old
  dc_state is released)

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Brian Chang &lt;Brian.Chang@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Limit HW cursor size of &gt;= 4k</title>
<updated>2022-11-23T14:47:13+00:00</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2022-11-09T14:27:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1f997af90102d99e14e59c72122ffa3a53752063'/>
<id>urn:sha1:1f997af90102d99e14e59c72122ffa3a53752063</id>
<content type='text'>
[Description]
- For SubVP, we cannot support HW cursor if it's
  greater than 64 x 64 x 4 bytes in size
- However, on certain config changes (i.e. pixel format)
  we can exit SubVP (then change to HW cursor) then re-enter
  SubVP without changing back to SW cursor because there is
  no SetCursorAttributes call
- To workaround this issue, limit the HW cursor size to be
  less than 64 x 64 x 4 bytes whenever the stream is &gt;= 4K
- Also ensure this W/A only affects DCN that supports SubVP

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Brian Chang &lt;Brian.Chang@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add margin on DRR vblank start for subvp</title>
<updated>2022-11-23T14:47:13+00:00</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2022-11-07T22:07:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ae7169a9a2edf915da436db57c71af7f3935feac'/>
<id>urn:sha1:ae7169a9a2edf915da436db57c71af7f3935feac</id>
<content type='text'>
[Description]
- Add margin for HUBP "jitter" for SubVp + DRR case
- Also do a min transition even if MPO is added on a
  non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR)

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Brian Chang &lt;Brian.Chang@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
