kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn314, branch v6.7

drm/amd/display: Update min Z8 residency time to 2100 for DCN314

2023-11-29T23:04:19+00:00

[Why] Some panels with residency period of 2054 exhibit flickering with Z8 at the end of the frame. [How] As a workaround, increase the limit to block these panels. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by: Syed Hassan Acked-by: Hamza Mahfooz Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amd/display: Disable SYMCLK32_SE RCO on DCN314

2023-10-26T23:02:13+00:00

[WHY] Currently causes some DP link layer failures, backing out until the failures are root caused. Reviewed-by: Nicholas Kazlauskas Acked-by: Roman Li Signed-off-by: Michael Strauss Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Set the DML2 attribute to false in all DCNs older than version 3.5

2023-10-26T22:41:22+00:00

When DML2 was introduced, it targeted only new DCN versions. For controlling which ASIC should use this new version of DML, it was introduced the using_dml2 attribute. To avoid ambiguities, this commit explicitly sets using_dml2 to false in all ASICs that do not support DML2. Cc: Vitaly Prosyak Cc: Roman Li Cc: Qingqing Zhuo Cc: Daniel Wheeler Cc: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Refactor HWSS into component folder

2023-10-09T21:00:09+00:00

[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung Acked-by: Tom Chung Signed-off-by: Mounika Adhuri Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Modify Vmin default value

2023-10-09T20:53:17+00:00

Fine tune the Vmin clock value Reviewed-by: Robin Chen Acked-by: Tom Chung Signed-off-by: Max Tseng Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: set stream gamut remap matrix to MPC for DCN3+

2023-09-26T21:00:22+00:00

dc->caps.color.mpc.gamut_remap says there is a post-blending color block for gamut remap matrix for DCN3 HW family and newer versions. However, those drivers still follow DCN10 programming that remap stream gamut_remap_matrix to DPP (pre-blending). To enable pre-blending and post-blending gamut_remap matrix supports at the same time, set stream gamut_remap to MPC and plane gamut_remap to DPP for DCN families that support both. It was tested using IGT KMS color tests for DRM CRTC CTM property and it preserves test results. Signed-off-by: Melissa Wen Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: augment display clock in dc_cap structure

2023-09-26T21:00:22+00:00

[Why] Allow dc report maximum display clock possible at vmin Reviewed-by: Wayne Lin Acked-by: Wayne Lin Signed-off-by: Max Tseng Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: switch DC over to the new DRM logging macros

2023-09-26T21:00:21+00:00

For multi-GPU systems it is difficult to tell which GPU a particular message is being printed for and that is undesirable because it complicates debugging efforts. Also, the new macros allow us to enable logging for particular parts of the codebase more selectively (since we no longer need to throw everything at DRM_DEBUG_KMS()). So, for the reasons outlined above we should switch to the new macros. We can accomplish this by using the existing DC_LOGGER code to pass around the relevant `struct drm_device` which will be fed to the new macros in logger_types.h. Also, we must get rid of all instances of the DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use the DC logger there and we can simply refer to the macros directly there instead. Reviewed-by: Rodrigo Siqueira Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Fix DP2.0 timing sync

2023-09-26T21:00:21+00:00

[Why] Triggering OTG sync before all OTG/HPO clock programming is complete causes timing sync to fail and a subsequent P-state hang. [How] Move DTB clock programming earlier in the sequence to enable_stream_timing. Reviewed-by: Ariel Bernstein Acked-by: Wayne Lin Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Update DCN314 for DCN35 support

2023-08-30T19:51:14+00:00

[Why & How] Update DCN314 files for DCN35 usage. Signed-off-by: Qingqing Zhuo Acked-by: Harry Wentland Signed-off-by: Alex Deucher