<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn314, branch v6.3</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-04-18T21:17:59+00:00</updated>
<entry>
<title>drm/amd/display: limit timing for single dimm memory</title>
<updated>2023-04-18T21:17:59+00:00</updated>
<author>
<name>Daniel Miess</name>
<email>Daniel.Miess@amd.com</email>
</author>
<published>2023-04-04T18:04:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1e994cc0956b8dabd1b1fef315bbd722733b8aa8'/>
<id>urn:sha1:1e994cc0956b8dabd1b1fef315bbd722733b8aa8</id>
<content type='text'>
[Why]
1. It could hit bandwidth limitdation under single dimm
memory when connecting 8K external monitor.
2. IsSupportedVidPn got validation failed with
2K240Hz eDP + 8K24Hz external monitor.
3. It's better to filter out such combination in
EnumVidPnCofuncModality
4. For short term, filter out in dc bandwidth validation.

[How]
Force 2K@240Hz+8K@24Hz timing validation false in dc.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Daniel Miess &lt;Daniel.Miess@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Disable HUBP/DPP PG on DCN314 for now</title>
<updated>2023-02-16T03:20:38+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2023-02-02T20:15:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b7c67f72408b11b922f23f06c7df0f6743a2e89d'/>
<id>urn:sha1:b7c67f72408b11b922f23f06c7df0f6743a2e89d</id>
<content type='text'>
[Why]
The DMCUB implementation required to workaround corruption is
not currently stable and may cause intermittent corruption or hangs.

[How]
Disable PG until the sequence is stable.

Reviewed-by: Hansen Dsouza &lt;hansen.dsouza@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove stutter only configurations</title>
<updated>2023-02-14T21:04:28+00:00</updated>
<author>
<name>Nasir Osman</name>
<email>nasir.osman@amd.com</email>
</author>
<published>2023-02-01T19:16:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=71c4ca2d3b079d0ba4d9b3033641fea906cebfb6'/>
<id>urn:sha1:71c4ca2d3b079d0ba4d9b3033641fea906cebfb6</id>
<content type='text'>
[why]
Newer ASICs such as DCN314 needs to allow for both self refresh and mem
clk switching rather than just self refresh only. Otherwise, we can see
some p-state hangs on ASICs that do support mem clk switching.

[how]
Added an allow_self_refresh_only flag for dcn30_internal_validate_bw
and created a validate_bw method for DCN314 with the allow_self_refresh_only
flag set to false (to support mem clk switching).

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Nasir Osman &lt;nasir.osman@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable P-state validation checks for DCN314</title>
<updated>2023-02-14T21:00:31+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2023-01-27T15:03:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=37d184b548db0f64d4a878960b2c6988b38a3e7e'/>
<id>urn:sha1:37d184b548db0f64d4a878960b2c6988b38a3e7e</id>
<content type='text'>
[Why]
To align with DCN31 behavior. This helps avoid p-state hangs in
the case where underflow does occur.

[How]
Flip the bit to true.

Reviewed-by: Hansen Dsouza &lt;hansen.dsouza@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Move DCN314 DOMAIN power control to DMCUB</title>
<updated>2023-02-14T20:47:20+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2023-01-23T19:59:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e383b12709e32d6494c948422070c2464b637e44'/>
<id>urn:sha1:e383b12709e32d6494c948422070c2464b637e44</id>
<content type='text'>
[Why]
DOMAIN power gating control is now required to be done via firmware
due to interlock with other power features. This is to avoid
intermittent issues in the LB memories.

[How]
If the firmware supports the command then use the new firmware as
the sequence can avoid potential display corruption issues.

The command will be ignored on firmware that does not support DOMAIN
power control and the pipes will remain always on - frequent PG cycling
can cause the issue to occur on the old sequence, so we should avoid it.

Reviewed-by: Hansen Dsouza &lt;hansen.dsouza@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: break down dc_link.c</title>
<updated>2023-02-08T22:15:51+00:00</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2023-01-18T22:31:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=54618888d1ea7a26f8bccfb89e3c2420350c8047'/>
<id>urn:sha1:54618888d1ea7a26f8bccfb89e3c2420350c8047</id>
<content type='text'>
[why]
dc_link contains over 30k line of code, the decision is to break it
down to files residing in link folder based on functionality. This
change is the last break down change which will remove dc_link.c
file after everything is broken down.

[how]
Move remaining dc_link.c functions into link_detection, link_dpms,
link_validation, link_resource, and link_fpga and remove dc_link.

Reviewed-by: George Shen &lt;George.Shen@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Adjust downscaling limits for dcn314</title>
<updated>2023-01-31T19:01:59+00:00</updated>
<author>
<name>Daniel Miess</name>
<email>Daniel.Miess@amd.com</email>
</author>
<published>2023-01-17T20:45:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ed9ca86b8c434f8f24355278f020a86bd445034f'/>
<id>urn:sha1:ed9ca86b8c434f8f24355278f020a86bd445034f</id>
<content type='text'>
[Why]
Lower max_downscale_ratio and ARGB888 downscale factor
to prevent cases where underflow may occur on dcn314

[How]
Set max_downscale_ratio to 400 and ARGB downscale factor
to 250 for dcn314

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Daniel Miess &lt;Daniel.Miess@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: merge dc_link_dp into dc_link</title>
<updated>2023-01-24T18:26:25+00:00</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2023-01-09T21:52:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6ca7415f11af5200ab10bd420b513f846e9bfb99'/>
<id>urn:sha1:6ca7415f11af5200ab10bd420b513f846e9bfb99</id>
<content type='text'>
[why]
Temporarly merge dc_link_dp functions into dc_link for the
purpose of removing dc_link_dp files. This is a transitional
change for later commits where we will further refactor dc_link
file.

Reviewed-by: George Shen &lt;George.Shen@amd.com&gt;
Acked-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable AdaptiveSync in DC interface</title>
<updated>2023-01-24T18:26:25+00:00</updated>
<author>
<name>Sung Joon Kim</name>
<email>sungjoon.kim@amd.com</email>
</author>
<published>2023-01-11T18:12:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e95afc1cf7c66e010ef47a0df729f1baf3199671'/>
<id>urn:sha1:e95afc1cf7c66e010ef47a0df729f1baf3199671</id>
<content type='text'>
[why]
Start enabling AdaptiveSync feature on Linux environment.

[how]
Adding AdaptiveSync support in DC layer
- building AdaptiveSync info_packets
- adjusting the v_startup parameter

Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Signed-off-by: Sung Joon Kim &lt;sungjoon.kim@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: contional remove disable dig_fifo when blank</title>
<updated>2023-01-17T20:40:20+00:00</updated>
<author>
<name>Charlene Liu</name>
<email>Charlene.Liu@amd.com</email>
</author>
<published>2022-12-21T00:46:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=40774ad1c460ada855068f67da549f78ecb136e8'/>
<id>urn:sha1:40774ad1c460ada855068f67da549f78ecb136e8</id>
<content type='text'>
keep dig_fifo enable for test pattern generation.

Tested-by: Daniel Wheeler &lt;Daniel.Wheeler@amd.com&gt;
Reviewed-by: Chris Park &lt;Chris.Park@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
