kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn30, branch v6.3

drm/amd/display: Do not set DRR on pipe Commit

2023-03-15T22:18:00+00:00

[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. Cc: stable@vger.kernel.org Cc: Mario Limonciello Reviewed-by: Jun Lei Acked-by: Qingqing Zhuo Signed-off-by: Wesley Chalmers Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

Revert "drm/amd/display: Do not set DRR on pipe commit"

2023-03-02T03:43:58+00:00

This reverts commit 4f1b5e739dfd1edde33329e3f376733a131fb1ff. [Why & How] Original change causes a regression. Revert until fix is available. Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo Signed-off-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: clean code-style issues in dcn30_set_mpc_shaper_3dlut

2023-02-16T03:20:32+00:00

This function has many conditions and all code style issues (identation, missing braces, etc.) make reading it really annoying. Reviewed-by: Christian König Signed-off-by: Melissa Wen Signed-off-by: Alex Deucher

drm/amd/display: ident braces in dcn30_acquire_post_bldn_3dlut correctly

2023-02-16T03:20:27+00:00

Reviewed-by: Christian König Signed-off-by: Melissa Wen Signed-off-by: Alex Deucher

drm/amd/display: Remove stutter only configurations

2023-02-14T21:04:28+00:00

[why] Newer ASICs such as DCN314 needs to allow for both self refresh and mem clk switching rather than just self refresh only. Otherwise, we can see some p-state hangs on ASICs that do support mem clk switching. [how] Added an allow_self_refresh_only flag for dcn30_internal_validate_bw and created a validate_bw method for DCN314 with the allow_self_refresh_only flag set to false (to support mem clk switching). Reviewed-by: Nicholas Kazlauskas Acked-by: Qingqing Zhuo Signed-off-by: Nasir Osman Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: break down dc_link.c

2023-02-08T22:15:51+00:00

[why] dc_link contains over 30k line of code, the decision is to break it down to files residing in link folder based on functionality. This change is the last break down change which will remove dc_link.c file after everything is broken down. [how] Move remaining dc_link.c functions into link_detection, link_dpms, link_validation, link_resource, and link_fpga and remove dc_link. Reviewed-by: George Shen Acked-by: Qingqing Zhuo Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher

drm/amd/display: Do not commit pipe when updating DRR

2023-02-08T22:15:21+00:00

[WHY] DRR and Pipe cannot be updated on the same frame, or else underflow will occur. Reviewed-by: Jun Lei Acked-by: Qingqing Zhuo Signed-off-by: Wesley Chalmers Signed-off-by: Alex Deucher

drm/amd/display: Do not set DRR on pipe commit

2023-02-08T22:15:14+00:00

[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. [HOW] Defer all DPP adjustment requests till optimized_required is false. Reviewed-by: Jun Lei Acked-by: Qingqing Zhuo Signed-off-by: Wesley Chalmers Signed-off-by: Alex Deucher

drm/amd/display: merge dc_link_dp into dc_link

2023-01-24T18:26:25+00:00

[why] Temporarly merge dc_link_dp functions into dc_link for the purpose of removing dc_link_dp files. This is a transitional change for later commits where we will further refactor dc_link file. Reviewed-by: George Shen Acked-by: Alan Liu Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Enable AdaptiveSync in DC interface

2023-01-24T18:26:25+00:00

[why] Start enabling AdaptiveSync feature on Linux environment. [how] Adding AdaptiveSync support in DC layer - building AdaptiveSync info_packets - adjusting the v_startup parameter Reviewed-by: Harry Wentland Reviewed-by: Anthony Koo Acked-by: Alan Liu Signed-off-by: Sung Joon Kim Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher