kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn302, branch v6.7

drm/amd/display: Set the DML2 attribute to false in all DCNs older than version 3.5

2023-10-26T22:41:22+00:00

When DML2 was introduced, it targeted only new DCN versions. For controlling which ASIC should use this new version of DML, it was introduced the using_dml2 attribute. To avoid ambiguities, this commit explicitly sets using_dml2 to false in all ASICs that do not support DML2. Cc: Vitaly Prosyak Cc: Roman Li Cc: Qingqing Zhuo Cc: Daniel Wheeler Cc: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Refactor HWSS into component folder

2023-10-09T21:00:09+00:00

[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung Acked-by: Tom Chung Signed-off-by: Mounika Adhuri Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: switch DC over to the new DRM logging macros

2023-09-26T21:00:21+00:00

For multi-GPU systems it is difficult to tell which GPU a particular message is being printed for and that is undesirable because it complicates debugging efforts. Also, the new macros allow us to enable logging for particular parts of the codebase more selectively (since we no longer need to throw everything at DRM_DEBUG_KMS()). So, for the reasons outlined above we should switch to the new macros. We can accomplish this by using the existing DC_LOGGER code to pass around the relevant `struct drm_device` which will be fed to the new macros in logger_types.h. Also, we must get rid of all instances of the DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use the DC logger there and we can simply refer to the macros directly there instead. Reviewed-by: Rodrigo Siqueira Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: add more pipe resource interfaces

2023-08-30T19:35:30+00:00

Redesign pipe resource interfaces in resource.h file. The new interface design addresses the issue with lack of pipe topology encapsulation and lack of pipe accessors. Reviewed-by: Jun Lei Acked-by: Hamza Mahfooz Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher

drm/amd/display: rename acquire_idle_pipe_for_layer to acquire_free_pipe_as_sec_dpp_pipe

2023-08-07T21:14:09+00:00

[why] Secondary DPP pipes are used for rendering secondary layers of planes. The name "for layer" doesn't make it obvious. The function is acquiring a free pipe as secondary dpp pipe only. We rename it so it is more obvious. In a future follow up change, we want to add functions to acquire free pipe as opp head pipe or otg master pipe as well. They will have their separate allocation priority. Reviewed-by: Jun Lei Acked-by: Tom Chung Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add structs for Freesync Panel Replay

2023-08-07T21:12:49+00:00

In some instances, the GPU is transmitting repeated frame to the sink without any updates or changes in the content. These repeat transmission are wasteful, resulting in power draw in different aspects of the system 1. DCN is fetching the frame of data from DF/UMC/DRAM. This memory traffic prevents power down of parts of this HW path. 2. GPU is transmitting pixel data to the display through the main link of the DisplayPort interface. This prevents power down of both the Source transmitter (TX) and the Sink receiver (RX) The concepts of utilizing replay is similar to PSR, but there is a benefit of: Source and Sink remaining synchronized which allows for - lower latency when switching from replay to live frames - enable the possibility of more use cases - easy control of the sink's refresh rate during replay Due to Source and Sink remaining timing synchronized, Replay can be activated in more UI scenarios. Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: enable the new fast update path for supported ASICs

2023-06-23T19:43:25+00:00

The new fast update sequence is now supported on some ASICs. So, enable it by default for all applicable ASICs. Reviewed-by: Samson Tam Acked-by: Hamza Mahfooz Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher

drm/amd/display: Limit Minimum FreeSync Refresh Rate

2023-06-15T14:44:49+00:00

Why: Some EDIDs report a minimum refresh rate lower than what HW can support How: Add a check to calculate minimum supported refresh rate with current timing and use that as the minimum if a lower one is passed in Acked-by: Stylon Wang Signed-off-by: Austin Zheng Reviewed-by: Anthony Koo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: remove unused definition

2023-06-09T15:07:48+00:00

Eliminate the following warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:957:43: warning: unused variable 'res_create_maximus_funcs' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn302/dcn302_resource.c:101:38: warning: unused variable 'debug_defaults_diags' Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5296 Fixes: 25879d7b4986 ("drm/amd/display: Clean FPGA code in dc") Signed-off-by: Yang Li Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Clean FPGA code in dc

2023-06-09T14:44:11+00:00

[Why] Drop dead code for Linux. [How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC Reviewed-by: Ariel Bernstein Acked-by: Tom Chung Signed-off-by: Qingqing Zhuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher