kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn301, branch v6.3.2

drm/amd/display: refactor ddc logic from dc_link_ddc to link_ddc

2023-01-13T19:57:40+00:00

[why] 1. Move dd_link_ddc functions to link_ddc. 2. Move link ddc functions declaration exposed in dc to link.h 3. Move link ddc functions declaration exposed in dm to dc_link.h 4. Remove i2caux_interface.h file Tested-by: Daniel Wheeler Reviewed-by: Jun Lei Acked-by: Rodrigo Siqueira Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher

drm/amd/display: patch cases with unknown plane state to prevent warning

2023-01-03T21:57:57+00:00

[Why] DCN301 resource function is missing function pointer to handle cases with unknown plane state. This causes assertion when global state is validated while using swizzle parameter as “DC_UNKNOWN” [How] Add function pointer to handle and patch cases when plane state is unknown. Acked-by: Aurabindo Pillai Signed-off-by: Swapnil Patel Reviewed-by: Sung joon Kim Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Enable dp_hdmi21_pcon support

2022-12-06T15:15:55+00:00

[Why] It is not enabled for DCN3.0.1, 3.0.2, 3.0.3. [How] Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions. Reviewed-by: Martin Leung Acked-by: Stylon Wang Signed-off-by: David Galiffi Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: rework macros for DWB register access

2022-11-15T18:35:15+00:00

[Why] A hack was used to access DWB register due to difference in the register naming convention which was not compatible with existing SR/SRI* macros. The additional macro needed were added to dwb ip specific header file (dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in turn needed us to undefine them in the resource file. [How] Add a separate macro for DWB access to the resource files that need it instead of defining them in DWB ip header file. This will enable us to reuse the BASE macro defined in the resource file. Reviewed-by: Roman Li Acked-by: Tom Chung Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Have risk for memory exhaustion

2022-11-09T22:41:42+00:00

In dcn*_clock_source_create when dcn*_clk_src_construct fails allocated clk_src needs release. A local attack could use this to cause memory exhaustion. Signed-off-by: LongJun Tang Signed-off-by: Alex Deucher

drm/amd/display: clean up one inconsistent indenting

2022-10-06T16:04:57+00:00

clean up one inconsistent indenting Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2321 Reported-by: Abaci Robot Signed-off-by: Yang Li Signed-off-by: Alex Deucher

drm/amd/display: Add debug option for exiting idle optimizations on cursor updates

2022-09-29T13:41:44+00:00

[Description] - Have option to exit idle opt on cursor updates for debug and optimizations purposes Reviewed-by: Aric Cyr Acked-by: Jasdeep Dhillon Signed-off-by: Brandon Syu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Removing 2 phys

2022-09-19T19:14:12+00:00

[WHY] New dcn301 has 2 less phys Reviewed-by: Charlene Liu Acked-by: Wayne Lin Signed-off-by: Pavle Kotarac Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: rework recent update PHY state commit

2022-09-19T19:10:24+00:00

[why] Original change 594b237b9a07 ("drm/amd/display: Add interface to track PHY state") was implemented by assuming stream's dpms off is equivalent to PHY power off. This assumption doesn't hold in following situations: 1. MST multiple stream scenario, where multiple streams are sharing the same PHY output. Toggle dpms off for one of the stream doesn't power off the PHY due to the presence of other streams. 2. enable stream failure scenario, where enable stream fails due to failure of link training. This will cause DPMS off is set to false, while the actual PHY power state is off in certain cases. Due to the problematic assumption, the logic will skip disabling other streams for MST multiple stream scenario, therefore PHY is not actually powered off. [how] 1. Rework this refactor by moving PHY state update down to hardware level, where we update PHY state in place when hardware sequencer is actually changing the power state of the PHY hardware. 2. Reimplement symclk on TX off workaround in place when we are actually calling transmitter control to power off PHY in dcn32. Note the workaround is added due to the lack of proper software interface to set TX while keeping symclk on. We plan to address this interface problem so we can set TX off only without affecting symclk in future dcn versions. Fixes: 594b237b9a07 ("drm/amd/display: Add interface to track PHY state") Reviewed-by: Jun Lei Acked-by: Wayne Lin Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add dc_ctx to link_enc_create() parameters

2022-07-25T21:17:28+00:00

[Why&How] Preparation to enable run time initialization of register offsets to add dc_context to the link_enc_create callback. This is needed to get the dc_ctx handle where register offset initialization routine is called. Reviewed-by: Rodrigo Siqueira Acked-by: Alan Liu Acked-by: Alex Hung Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher