kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn21, branch v6.2

drm/amd/display: Fix spelling mistake: "dram_clk_chanage" -> "dram_clk_change"

2022-12-09T21:50:30+00:00

There is a spelling mistake in the struct field dram_clk_chanage. Fix it. Signed-off-by: Colin Ian King Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: rework macros for DWB register access

2022-11-15T18:35:15+00:00

[Why] A hack was used to access DWB register due to difference in the register naming convention which was not compatible with existing SR/SRI* macros. The additional macro needed were added to dwb ip specific header file (dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in turn needed us to undefine them in the resource file. [How] Add a separate macro for DWB access to the resource files that need it instead of defining them in DWB ip header file. This will enable us to reuse the BASE macro defined in the resource file. Reviewed-by: Roman Li Acked-by: Tom Chung Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Refactor eDP PSR codes

2022-10-24T18:35:54+00:00

We split out PSR config from "global" to "per-panel" config settings. Tested-by: Mark Broadworth Reviewed-by: Robin Chen Acked-by: Rodrigo Siqueira Signed-off-by: Ian Chen Signed-off-by: Alex Deucher

drm/amd/display: Refactor edp ILR caps codes

2022-10-06T16:00:02+00:00

We split out ILR config from "global" to "per-panel" config settings. Reviewed-by: Anthony Koo Acked-by: Hamza Mahfooz Signed-off-by: Ian Chen Signed-off-by: Alex Deucher

drm/amd/display: prevent S4 test from failing

2022-10-06T15:59:14+00:00

[why] limit the vm prefetch check for now, until the feature is fully verified. Reviewed-by: Hansen Dsouza Acked-by: Hamza Mahfooz Signed-off-by: Charlene Liu Signed-off-by: Alex Deucher

drm/amd/display: rework recent update PHY state commit

2022-09-19T19:10:24+00:00

[why] Original change 594b237b9a07 ("drm/amd/display: Add interface to track PHY state") was implemented by assuming stream's dpms off is equivalent to PHY power off. This assumption doesn't hold in following situations: 1. MST multiple stream scenario, where multiple streams are sharing the same PHY output. Toggle dpms off for one of the stream doesn't power off the PHY due to the presence of other streams. 2. enable stream failure scenario, where enable stream fails due to failure of link training. This will cause DPMS off is set to false, while the actual PHY power state is off in certain cases. Due to the problematic assumption, the logic will skip disabling other streams for MST multiple stream scenario, therefore PHY is not actually powered off. [how] 1. Rework this refactor by moving PHY state update down to hardware level, where we update PHY state in place when hardware sequencer is actually changing the power state of the PHY hardware. 2. Reimplement symclk on TX off workaround in place when we are actually calling transmitter control to power off PHY in dcn32. Note the workaround is added due to the lack of proper software interface to set TX while keeping symclk on. We plan to address this interface problem so we can set TX off only without affecting symclk in future dcn versions. Fixes: 594b237b9a07 ("drm/amd/display: Add interface to track PHY state") Reviewed-by: Jun Lei Acked-by: Wayne Lin Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: avoid doing vm_init multiple time

2022-08-16T22:09:16+00:00

[why] this is to ensure that driver will not reprogram hvm_prefetch_req again if it is done. Reviewed-by: Martin Leung Acked-by: Brian Chang Signed-off-by: Charlene Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add dc_ctx to link_enc_create() parameters

2022-07-25T21:17:28+00:00

[Why&How] Preparation to enable run time initialization of register offsets to add dc_context to the link_enc_create callback. This is needed to get the dc_ctx handle where register offset initialization routine is called. Reviewed-by: Rodrigo Siqueira Acked-by: Alan Liu Acked-by: Alex Hung Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: rename hdmi_frl_pcon_support

2022-07-05T20:17:39+00:00

hdmi_frl_pcon_support has been the source of confusion. So, rename it to dp_hdmi21_pcon_support. Signed-off-by: Hamza Mahfooz Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix memory leak in dcn21_clock_source_create

2022-04-21T19:59:52+00:00

When dcn20_clk_src_construct() fails, we need to release clk_src. Fixes: 6f4e6361c3ff ("drm/amd/display: Add Renoir resource (v2)") Signed-off-by: Miaoqian Lin Signed-off-by: Alex Deucher