kernel/linux.git/drivers/gpu/drm/amd/display/dc/dcn20, branch v6.7

drm/amd/display: fix hw rotated modes when PSR-SU is enabled

2023-12-11T17:41:05+00:00

We currently don't support dirty rectangles on hardware rotated modes. So, if a user is using hardware rotated modes with PSR-SU enabled, use PSR-SU FFU for all rotated planes (including cursor planes). Cc: stable@vger.kernel.org Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support") Reported-by: Kai-Heng Feng Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2952 Tested-by: Kai-Heng Feng Tested-by: Bin Li Reviewed-by: Mario Limonciello Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Allow 16 max_slices for DP2 DSC

2023-11-07T16:17:03+00:00

Enable 12 and 16 max_slices for DP2 DSC Reviewed-by: Alvin Lee Acked-by: Hersen Wu Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Set the DML2 attribute to false in all DCNs older than version 3.5

2023-10-26T22:41:22+00:00

When DML2 was introduced, it targeted only new DCN versions. For controlling which ASIC should use this new version of DML, it was introduced the using_dml2 attribute. To avoid ambiguities, this commit explicitly sets using_dml2 to false in all ASICs that do not support DML2. Cc: Vitaly Prosyak Cc: Roman Li Cc: Qingqing Zhuo Cc: Daniel Wheeler Cc: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Refactor HWSS into component folder

2023-10-09T21:00:09+00:00

[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung Acked-by: Tom Chung Signed-off-by: Mounika Adhuri Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Move the memory allocation out of dcn20_validate_bandwidth_fp().

2023-10-09T20:48:08+00:00

dcn20_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. To preserve previous "clean" state of "pipes" add a memset() before the second invocation of dcn20_validate_bandwidth_internal() where the variable is used. Acked-by: Harry Wentland Reviewed-by: Rodrigo Siqueira Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Adjust code style for hw_sequencer.h

2023-10-04T22:42:41+00:00

[Why&How] * Rearrange some definitions for consistency * Drop legacy code Signed-off-by: Aurabindo Pillai Reviewed-by: Rodrigo Siqueira Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: fix incorrect odm change detection logic

2023-09-26T21:00:22+00:00

[why] The current ODM change detection only compares first two ODM slices. If there are 4 ODM slices and the change is within the last two slices, the logic fails to detect ODM change and cause us to skip ODM programming unexpectedly. [how] Add a is ODM topology changed resource interface to check any ODM topology changes with a more generic method. Reviewed-by: Dillon Varone Acked-by: Wayne Lin Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: switch DC over to the new DRM logging macros

2023-09-26T21:00:21+00:00

For multi-GPU systems it is difficult to tell which GPU a particular message is being printed for and that is undesirable because it complicates debugging efforts. Also, the new macros allow us to enable logging for particular parts of the codebase more selectively (since we no longer need to throw everything at DRM_DEBUG_KMS()). So, for the reasons outlined above we should switch to the new macros. We can accomplish this by using the existing DC_LOGGER code to pass around the relevant `struct drm_device` which will be fed to the new macros in logger_types.h. Also, we must get rid of all instances of the DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use the DC logger there and we can simply refer to the macros directly there instead. Reviewed-by: Rodrigo Siqueira Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Fix DP2.0 timing sync

2023-09-26T21:00:21+00:00

[Why] Triggering OTG sync before all OTG/HPO clock programming is complete causes timing sync to fail and a subsequent P-state hang. [How] Move DTB clock programming earlier in the sequence to enable_stream_timing. Reviewed-by: Ariel Bernstein Acked-by: Wayne Lin Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: fix some style issues

2023-09-26T20:54:51+00:00

Fixes a few style issues: - Only calculate the dto_params and dp_hpo_inst when dccg is present. - Fix indentation - Drop empty else block Fixes: 7f7925e25828 ("drm/amd/display: Fix MST recognizes connected displays as one") Cc: Muhammad Ahmed Cc: Michel Dänzer Cc: Stylon Wang Reviewed-by: Hamza Mahfooz Signed-off-by: Alex Deucher