<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/dce, branch v7.2-rc1</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc1</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc1'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-06-03T17:44:46+00:00</updated>
<entry>
<title>drm/amd/display: Add support for FRL to DC core</title>
<updated>2026-06-03T17:44:46+00:00</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2026-04-24T18:23:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=fdaf63d9a83aeff2f165b45e7073767bbe62f2fc'/>
<id>urn:sha1:fdaf63d9a83aeff2f165b45e7073767bbe62f2fc</id>
<content type='text'>
Here we add support for reading BIOS caps and tie FRL bits
into the rest of DC core.

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add no_native_i2c codepath</title>
<updated>2026-06-03T17:43:29+00:00</updated>
<author>
<name>Matthew Stewart</name>
<email>Matthew.Stewart2@amd.com</email>
</author>
<published>2026-05-19T01:34:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6750a2316f3f3b34016bcc425a0e99af1efb1c58'/>
<id>urn:sha1:6750a2316f3f3b34016bcc425a0e99af1efb1c58</id>
<content type='text'>
[Why]
ASICs which do not have native DDC capability must use a different
codepath to access the AUX channel.

[How]
- BIOS cap NO_DDC_PIN is set to 1 for links which do not have the DDC pin.
- dp_connector_no_native_i2c in dc_config must also be set to true to
  use this codepath.

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;Matthew.Stewart2@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix DP_PIXEL_FORMAT fields &amp; update clk_src for DCN4x</title>
<updated>2026-06-03T17:39:58+00:00</updated>
<author>
<name>Ovidiu Bunea</name>
<email>ovidiu.bunea@amd.com</email>
</author>
<published>2026-05-14T21:39:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c2572d535be4847f8caba58b4ee8446b4ee15b57'/>
<id>urn:sha1:c2572d535be4847f8caba58b4ee8446b4ee15b57</id>
<content type='text'>
[Why &amp; How]
The enc1_stream_encoder_dp_get_pixel_format() function reads fields of the
DP_PIXEL_FORMAT register that are deprecated on DCN4x. This breaks seamless
boot because driver cannot properly determine the pixel format programmed by VBIOS.
The previous changed submitted for this issue incorrectly calculated the DP DTO
frequency because register access to DCN4x DP DTO registers was not working.

Create a new function that reads the correct fields.
Update clk_src structs to support register access for new DCN4x registers &amp; fields.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Ovidiu Bunea &lt;ovidiu.bunea@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add missing CSC entries for BT.2020 for DCE IPs</title>
<updated>2026-06-03T17:31:32+00:00</updated>
<author>
<name>Leorize</name>
<email>leorize+oss@disroot.org</email>
</author>
<published>2026-05-28T06:58:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=51e6668ab4baf55b082c376318d51ef965757196'/>
<id>urn:sha1:51e6668ab4baf55b082c376318d51ef965757196</id>
<content type='text'>
DCE-based hardware does not have the CSC matrices for BT.2020, which
causes the driver to fallback to the GPU built-in matrices. This does
not appear to cause any issues for RGB sinks, but causes major color
artifacts for YCbCr ones (e.g. black becomes green).

This commit adds the missing CSC matrices (taken from DC common) to DCE
CSC tables, resolving the issue.

Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/3358
Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5333
Assisted-by: oh-my-pi:GPT-5.5
Signed-off-by: Leorize &lt;leorize+oss@disroot.org&gt;
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Update get_pixel_clk_frequency() for DCN4x DCCG DP DTO</title>
<updated>2026-06-03T17:31:08+00:00</updated>
<author>
<name>Ovidiu Bunea</name>
<email>ovidiu.bunea@amd.com</email>
</author>
<published>2026-05-01T23:38:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6f6483dbfacd2269da68cb97db996c0f31f650f2'/>
<id>urn:sha1:6f6483dbfacd2269da68cb97db996c0f31f650f2</id>
<content type='text'>
[Why &amp; How]
DCN4x ASICs have different DCCG logic for programming DP DTO. The current
get_pixel_clk_frequency_100hz() function does not account for this.

Rename the function to "get_dp_dto_frequency" to more accurately
reflect its intended behaviour. Create a new function that correctly
calculates the target pixel rate for DCN4.x DCCG design and use it.

Reviewed-by: Leo Chen &lt;leo.chen@amd.com&gt;
Signed-off-by: Ovidiu Bunea &lt;ovidiu.bunea@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactor dc_link_aux_transfer_raw</title>
<updated>2026-05-11T20:10:41+00:00</updated>
<author>
<name>Matthew Stewart</name>
<email>Matthew.Stewart2@amd.com</email>
</author>
<published>2026-04-02T21:42:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=615c3102e9673910b9dd160b3a8267657f8907b9'/>
<id>urn:sha1:615c3102e9673910b9dd160b3a8267657f8907b9</id>
<content type='text'>
[Why &amp; How]
The logic for choosing between the dce_aux_transfer function variants is
moved into dce_aux.c rather than link_ddc.c.

The "dce_aux_transfer_with_retries" function now uses
dce_aux_transfer_raw in its implementation as the logic is equivalent.

Reviewed-by: Nevenko Stupar &lt;nevenko.stupar@amd.com&gt;
Reviewed-by: Gabe Teeger &lt;gabe.teeger@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;Matthew.Stewart2@amd.com&gt;
Signed-off-by: James Lin &lt;pinglei.lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix type mismatches using guards and explicit casts</title>
<updated>2026-05-05T13:56:52+00:00</updated>
<author>
<name>Gaghik Khachatrian</name>
<email>gaghik.khachatrian@amd.com</email>
</author>
<published>2026-04-21T16:24:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=64b4c4cdfddd31d3a0ec468afccb7ff7cd926682'/>
<id>urn:sha1:64b4c4cdfddd31d3a0ec468afccb7ff7cd926682</id>
<content type='text'>
[Why]
Address signed/unsigned comparison warnings across dc paths to keep
builds warning-clean and improve type safety at comparison boundaries.
Most warnings came from signed loop/index temporaries compared against
unsigned counters and table sizes, plus a smaller number of mixed
signed/unsigned clock, bandwidth, and geometry comparisons.

[How]
Aligned iterator and temporary variable types with the semantic type
of the compared bounds. Used unsigned indices for loops bounded by unsigned
counters and table sizes, while retaining signed types where values are
semantically signed or participate in arithmetic that may legitimately go
negative. Where mixed signed/unsigned comparisons are intentional, applied
explicit boundary casts or guarded comparisons instead of broad type
changes.

No functional behavior changes are intended; this is a warning-resolution
and type-alignment cleanup.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Gaghik Khachatrian &lt;gaghik.khachatrian@amd.com&gt;
Signed-off-by: James Lin &lt;pinglei.lin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Allow DCE link encoder without AUX registers</title>
<updated>2026-04-29T14:28:50+00:00</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2026-04-28T11:40:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=87f30b101af62590faf6020d106da07efdda199b'/>
<id>urn:sha1:87f30b101af62590faf6020d106da07efdda199b</id>
<content type='text'>
Allow constructing the DCE link encoder without DDC,
which means the AUX registers array will be NULL.

This is necessary to support embedded connectors without DDC.

Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/5192
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix narrowing boundaries and eDP parser assignment</title>
<updated>2026-04-17T19:41:16+00:00</updated>
<author>
<name>Gaghik Khachatrian</name>
<email>gaghik.khachatrian@amd.com</email>
</author>
<published>2026-04-09T03:02:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a4702db211806757fdd53fc79b753f30439a2f49'/>
<id>urn:sha1:a4702db211806757fdd53fc79b753f30439a2f49</id>
<content type='text'>
[Why] drm/amd/display had implicit integer narrowing at protocol/storage boundaries
and an incomplete eDP assignment in integrated info parsing.

[How] Apply explicit boundary casts for intentional narrowing, keep intermediate math
in wider types, and restore explicit eDP field mapping in v2.2 parser.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Gaghik Khachatrian &lt;gaghik.khachatrian@amd.com&gt;
Signed-off-by: Chenyu Chen &lt;chen-yu.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix implicit narrowing conversion warnings</title>
<updated>2026-04-17T19:41:15+00:00</updated>
<author>
<name>Gaghik Khachatrian</name>
<email>gaghik.khachatrian@amd.com</email>
</author>
<published>2026-03-31T23:14:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f4cdbb5d54057838b14a9b537309df24f20232c2'/>
<id>urn:sha1:f4cdbb5d54057838b14a9b537309df24f20232c2</id>
<content type='text'>
[Why]
Multiple display source files contain implicit narrowing
conversions when assigning wider integer types (int, uint32_t)
to narrower fields (uint8_t, uint16_t) at hardware register,
protocol, and storage boundaries. These conversions are
intentional but undocumented, and accompanying runtime assertions
add noise without providing compile-time safety.

[How]
Add explicit casts at all intentional narrowing boundaries across
display source files. Use narrower loop variable types where loop
bounds guarantee safe range. Remove runtime assertions paired
with narrowing casts, inline single-use intermediate variables,
and revert block scopes and braces introduced solely to contain
those assertions.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Gaghik Khachatrian &lt;gaghik.khachatrian@amd.com&gt;
Signed-off-by: Chenyu Chen &lt;chen-yu.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
