kernel/linux.git/drivers/gpu/drm/amd/display/dc/dce, branch v5.4.209

drm/amd/display: Fix HDMI deep color output for DCE 6-11.

2021-03-04T09:26:22+00:00

[ Upstream commit efa18405baa55a864c61d2f3cc6fe4d363818eb3 ] This fixes corrupted display output in HDMI deep color 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3. It will hopefully also provide fixes for other DCE's up to DCE-11, assuming those will need similar fixes, but i could not test that for HDMI due to lack of suitable hw, so viewer discretion is advised. dce110_stream_encoder_hdmi_set_stream_attribute() is used for HDMI setup on all DCE's and is missing color_depth assignment. dce110_program_pix_clk() is used for pixel clock setup on HDMI for DCE 6-11, and is missing color_depth assignment. Additionally some of the underlying Atombios specific encoder and pixelclock setup functions are missing code which is in the classic amdgpu kms modesetting path and the in the radeon kms driver for DCE6/DCE8. encoder_control_digx_v3() - Was missing setup code wrt. amdgpu and radeon kms classic drivers. Added here, but untested due to lack of suitable test hw. encoder_control_digx_v4() - Added missing setup code. Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color output at 10 bpc and 12 bpc. Note that encoder_control_digx_v5() has proper setup code in place and is used, e.g., by DCE-11.2, but this code wasn't used for deep color setup due to the missing cntl.color_depth setup in the calling function for HDMI. set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon kms. Added here, but untested due to lack of hw. set_pixel_clock_v6() - Missing setup code added. Successfully tested on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI deep color output with 10 bpc or 12 bpc. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Reviewed-by: Nicholas Kazlauskas Signed-off-by: Mario Kleiner Cc: Harry Wentland Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fix 10/12 bpc setup in DCE output bit depth reduction.

2021-03-04T09:26:22+00:00

[ Upstream commit 1916866dfa4aaceba1a70db83fde569387649d93 ] In set_clamp(), the comments and definitions for the COLOR_DEPTH_101010 and COLOR_DEPTH_121212 cases directly contradict the code comment which explains how this should work, whereas the COLOR_DEPTH_888 case is consistent with the code comments. Comment says the bitmask should be chosen to align to the top-most 10 or 12 MSB's on a 14 bit bus, but the implementation contradicts that: 10 bit case sets a mask for 12 bpc clamping, whereas 12 bit case sets a mask for 14 bpc clamping. Note that during my limited testing on DCE-8.3 (HDMI deep color) and DCE-11.2 (DP deep color), this didn't have any obvious ill effects, neither did fixing it change anything obvious for the better, so this fix may be inconsequential on DCE, and just reduce the confusion of innocent bystanders when reading the code and trying to investigate problems with 10 bpc+ output. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Mario Kleiner Cc: Harry Wentland Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Check engine is not NULL before acquiring

2020-03-05T15:43:38+00:00

[ Upstream commit 2b63d0ec0daf79ba503fa8bfa25e07dc3da274f3 ] [Why] Engine can be NULL in some cases, so we must not acquire it. [How] Check for NULL engine before acquiring. Signed-off-by: Aric Cyr Reviewed-by: Harry Wentland Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: wait for set pipe mcp command completion

2019-12-31T15:44:02+00:00

[ Upstream commit 15caeabc5787c15babad7ee444afe9c26df1c8b3 ] [Why] When the driver sends a pipe set command to the DMCU FW, it does not wait for the command to complete. This can lead to unpredictable behavior if, for example, the driver were to request a pipe disable to the FW via MCP, then power down some hardware before the firmware has completed processing the command. [How] Wait for the DMCU FW to finish processing set pipe commands Signed-off-by: Josip Pavic Reviewed-by: Anthony Koo Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: dce11.x /dce12 update formula input

2019-09-17T19:35:41+00:00

[Description] 1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update) 2. using memory type to convert UMC's MCLK to Yclk. Signed-off-by: Charlene Liu Reviewed-by: Dmytro Laktyushkin Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Fix register names

2019-08-29T20:52:33+00:00

rename VM_CONTEXT0 to MMVM_CONTEXT0 as that is the name defined in the register files Acked-by: Harry Wentland Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Add Renoir hw_seq register list

2019-08-29T20:52:32+00:00

These are the registers used to for the hw sequences for modesetting. Acked-by: Harry Wentland Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Add Renoir clock registers list

2019-08-29T20:52:32+00:00

These are the registers used to program the clock hw. Acked-by: Harry Wentland Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL

2019-08-23T16:45:55+00:00

[Why] The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the embedded display. Currently we do not actually read this register's values, so during power down we think that this display is already off, so we skip calling into VBIOS to actually turn it off. [How] - add relevant fields to shift / mask initialization Signed-off-by: Joshua Aberback Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Use res_cap to acquire i2c instead of pipe count

2019-08-23T16:45:34+00:00

[Why] We should be using the ddc_num from res_caps. As the pipe count != number of i2c resources. [How] Use ddc_num from res_cap instead of pipe count. Signed-off-by: Derek Lai Reviewed-by: Charlene Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher