<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/display/dc/dce, branch v5.10.7</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v5.10.7</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v5.10.7'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2021-01-06T13:56:49+00:00</updated>
<entry>
<title>drm/amd/display: Add get_dig_frontend implementation for DCEx</title>
<updated>2021-01-06T13:56:49+00:00</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2020-12-15T15:33:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8b8a688260b4ad39832d3fce790f2b53f1f3e535'/>
<id>urn:sha1:8b8a688260b4ad39832d3fce790f2b53f1f3e535</id>
<content type='text'>
commit 6bdeff12a96c9a5da95c8d11fefd145eb165e32a upstream.

Some old ASICs might not implement/require get_dig_frontend helper; in
this scenario, we can have a NULL pointer exception when we try to call
it inside vbios disable operation. For example, this situation might
happen when using Polaris12 with an eDP panel. This commit avoids this
situation by adding a specific get_dig_frontend implementation for DCEx.

Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Cc: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Cc: Chiawen Huang &lt;chiawen.huang@amd.com&gt;
Reported-and-tested-by: Borislav Petkov &lt;bp@suse.de&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;


</content>
</entry>
<entry>
<title>drm/amd/display: Fixed panic during seamless boot.</title>
<updated>2020-10-26T21:10:27+00:00</updated>
<author>
<name>David Galiffi</name>
<email>David.Galiffi@amd.com</email>
</author>
<published>2020-04-29T17:31:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=866e09f0110c6e86071954033e3067975946592a'/>
<id>urn:sha1:866e09f0110c6e86071954033e3067975946592a</id>
<content type='text'>
[why]
get_pixel_clk_frequency_100hz is undefined in clock_source_funcs.

[how]
set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz"

Signed-off-by: David Galiffi &lt;David.Galiffi@amd.com&gt;
Reviewed-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Ensure all debug bits are passed to fw</title>
<updated>2020-09-29T20:08:37+00:00</updated>
<author>
<name>Wyatt Wood</name>
<email>wyatt.wood@amd.com</email>
</author>
<published>2020-09-25T14:54:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=89b151ade71495ebe2e48923812571e8e6a92918'/>
<id>urn:sha1:89b151ade71495ebe2e48923812571e8e6a92918</id>
<content type='text'>
[Why]
Some debug bits are not being copied from driver to fw.

[How]
Copy debug bits properly.

Signed-off-by: Wyatt Wood &lt;wyatt.wood@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Implement PSR wait for enable/disable</title>
<updated>2020-09-22T16:28:49+00:00</updated>
<author>
<name>Wyatt Wood</name>
<email>wyatt.wood@amd.com</email>
</author>
<published>2020-09-11T01:50:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a9edc81564c92b4d86670b722bbe8906e0dfd934'/>
<id>urn:sha1:a9edc81564c92b4d86670b722bbe8906e0dfd934</id>
<content type='text'>
[Why]
For DMUB implementation of PSR, the 'wait' parameter,
used to determine if driver should wait for PSR enable/disable,
is not implemented correctly.

[How]
Implement wait for PSR enable/disable.

Signed-off-by: Wyatt Wood &lt;wyatt.wood@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Bug in dce_is_panel_backlight_on()</title>
<updated>2020-09-22T16:27:35+00:00</updated>
<author>
<name>Peikang Zhang</name>
<email>peikang.zhang@amd.com</email>
</author>
<published>2020-09-03T17:45:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=cbf229bbcb7fcc5f4f75f64eee7e224aa1b31ad2'/>
<id>urn:sha1:cbf229bbcb7fcc5f4f75f64eee7e224aa1b31ad2</id>
<content type='text'>
[Why]
dce_is_panel_backlight_on() will return wrong value if
LVTMA_BLON_OVRD is 0

[How]
When LVTMA_BLON_OVRD is 0, read
LVTMA_PWRSEQ_TARGET_STATE instead

Signed-off-by: Peikang Zhang &lt;peikang.zhang@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix incorrect backlight register offset for DCN</title>
<updated>2020-09-22T16:27:10+00:00</updated>
<author>
<name>David Galiffi</name>
<email>David.Galiffi@amd.com</email>
</author>
<published>2020-09-03T23:20:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=651111be24aa4c8b62c10f6fff51d9ad82411249'/>
<id>urn:sha1:651111be24aa4c8b62c10f6fff51d9ad82411249</id>
<content type='text'>
[Why]
Typo in backlight refactor introduced wrong register offset.

[How]
SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).

Signed-off-by: David Galiffi &lt;David.Galiffi@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: &lt;stable@vger.kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Rename set_mst_bandwidth to align with DP spec</title>
<updated>2020-09-15T21:52:41+00:00</updated>
<author>
<name>George Shen</name>
<email>george.shen@amd.com</email>
</author>
<published>2020-08-18T22:42:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6c95320d01dcac321e9e89903a26a840838a0ef6'/>
<id>urn:sha1:6c95320d01dcac321e9e89903a26a840838a0ef6</id>
<content type='text'>
[Why]
The function set_mst_bandwidth is poorly name since it isn't clear what
it does, and it also does not reflect any part of the allocation sequence
described in the DP spec.

[How]
Rename the function set_mst_bandwidth to set_throttled_vcp_size.

Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix potential integer overflow when shifting 32 bit variable bl_pwm</title>
<updated>2020-08-18T22:22:43+00:00</updated>
<author>
<name>Colin Ian King</name>
<email>colin.king@canonical.com</email>
</author>
<published>2020-08-18T12:09:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1d5503331b12a76266049289747dfd94f1643fde'/>
<id>urn:sha1:1d5503331b12a76266049289747dfd94f1643fde</id>
<content type='text'>
The 32 bit unsigned integer bl_pwm is being shifted using 32 bit arithmetic
and then being assigned to a 64 bit unsigned integer.  There is a potential
for a 32 bit overflow so cast bl_pwm to enforce a 64 bit shift operation
to avoid this.

Addresses-Coverity: ("unintentional integer overflow")
Fixes: 3ba01817365c ("drm/amd/display: Move panel_cntl specific register from abm to panel_cntl.")
Signed-off-by: Colin Ian King &lt;colin.king@canonical.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add read backlight interface</title>
<updated>2020-08-17T18:08:12+00:00</updated>
<author>
<name>Yongqiang Sun</name>
<email>yongqiang.sun@amd.com</email>
</author>
<published>2020-08-05T15:34:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ccc875052f829a03d1c9f67fc3a8709fe6c67c31'/>
<id>urn:sha1:ccc875052f829a03d1c9f67fc3a8709fe6c67c31</id>
<content type='text'>
[Why &amp; How]
Add read backlight interface to get ABM data.

Signed-off-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix incorrect backlight register offset for DCN</title>
<updated>2020-08-10T21:26:52+00:00</updated>
<author>
<name>Aric Cyr</name>
<email>aric.cyr@amd.com</email>
</author>
<published>2020-07-28T01:21:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5396fa590df764775e83c9014330bc4112a75f63'/>
<id>urn:sha1:5396fa590df764775e83c9014330bc4112a75f63</id>
<content type='text'>
[Why]
Typo in backlight refactor inctroduced wrong register offset.

[How]
Change DCE to DCN register map for PWRSEQ_REF_DIV

Cc: stable@vger.kernel.org
Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Reviewed-by: Ashley Thomas &lt;Ashley.Thomas2@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
