kernel/linux.git/drivers/gpu/drm/amd/display/dc/dce, branch linux-6.0.y

drm/amd/display: Fix pixel clock programming

2022-08-16T22:07:21+00:00

[Why] Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned between different HDMI lanes when using YCbCr420 10-bit pixel format. BIOS functions for transmitter/encoder control take pixel clock in kHz increments, whereas the function for setting the pixel clock is in 100Hz increments. Setting pixel clock to a value that is not on a kHz boundary will cause the issue. [How] Round pixel clock down to nearest kHz in 10/12-bpc cases. Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amdgpu/dc/dce: fix repeated words in comments

2022-07-28T20:05:14+00:00

Delete the redundant word 'in'. Signed-off-by: wangjianli Signed-off-by: Alex Deucher

drm/amd/display: Use correct DTO_SRC_SEL for 128b/132b encoding

2022-07-25T21:16:45+00:00

[WHY] DP DTO isn't used for 128b/132b encoding [HOW] Check current link rate to determine whether using 8b/10b or 128/132b encoding Reviewed-by: Nicholas Kazlauskas Acked-by: Alex Hung Signed-off-by: Michael Strauss Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Remove unused clk_src variable

2022-07-25T13:31:02+00:00

Remove the variable clk_src from the function dcn3_get_pix_clk_dividers. This was pointed by clang with the following warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.c:1279:25: warning: variable 'clk_src' set but not used [-Wunused-but-set-variable] struct dce110_clk_src *clk_src; ^ 1 warning generated. Reviewed-by: André Almeida Signed-off-by: Maíra Canal Signed-off-by: Alex Deucher

drm/amd/display: Enable DCN314 in DC

2022-07-14T00:57:05+00:00

Add support for DCN 3.1.4 in Display Core Signed-off-by: Roman Li Signed-off-by: Alex Deucher

drm/amd/display: Move all linux includes into OS types

2022-07-05T20:16:49+00:00

Move all linux includes into OS types. Acked-by: Alan Liu Signed-off-by: Harry Wentland Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Guard against ddc_pin being NULL for AUX

2022-07-05T20:13:27+00:00

[Why] In the case where we don't support DMUB aux but we have DPIA links in the configuration we might try to message AUX using the legacy path - where DDC pin is NULL. This causes a NULL pointer dereference. [How] Guard against NULL DDC pin, return a failure for aux engine acquire. Reviewed-by: Michael Strauss Acked-by: Rodrigo Siqueira Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Program ACP related register

2022-07-05T20:13:18+00:00

- Setup the shift and mask of HDMI_ACP_SEND register - Program the register in hdmi stream encoder - Also update ACP register in azalia configuration Reviewed-by: Harry Wentland Acked-by: Rodrigo Siqueira Signed-off-by: Alan Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add PSR-SU-RC support in DC

2022-06-07T20:09:57+00:00

[Why] PSR-SU Rate Control - or PSR-SU-RC - enables PSR-SU panels to work with variable refresh rate to allow for more power savings. Lowering the refresh rate can increase PSR residency by expanding the eDP main link shut down duration. It can also lower panel power consumption. There is a complication with PSR, since the eDP main link can be shut down. Therefore, the timing controller (TCON) on the eDP sink nees to be able to scan out its remote buffer independent of the main link. To allow the eDP source to specify the sink's refresh rate while the link is off, vendor-specific DPCD registers are used. This allows the eDP source to then "Rate Control" the panel during PSR active. [How] Add DC support to communicate with PSR-SU-RC supported eDP sinks. The sink will need to know the desired VTotal during PSR active. This change only adds support to DC, support in amdgpu_dm is still pending to enable this fully. Signed-off-by: David Zhang Signed-off-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: PSRSU+DSC WA for specific TCON

2022-06-06T18:42:27+00:00

[why] Some specific TCON chip has HW limitation to support PSRSU+DSC. [how] Force ffu mode when DSC enabled if we detect it is the specific model from sink OUI DPCD. And disable ABM update for this case. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher