kernel/linux.git/drivers/gpu/drm/amd/display/dc/dce, branch linux-5.9.y

drm/amd/display: Fixed panic during seamless boot.

2020-11-10T11:39:05+00:00

[ Upstream commit 866e09f0110c6e86071954033e3067975946592a ] [why] get_pixel_clk_frequency_100hz is undefined in clock_source_funcs. [how] set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz" Signed-off-by: David Galiffi Reviewed-by: Bhawanpreet Lakha Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fix incorrect backlight register offset for DCN

2020-11-05T10:51:48+00:00

commit 651111be24aa4c8b62c10f6fff51d9ad82411249 upstream. [Why] Typo in backlight refactor introduced wrong register offset. [How] SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2). Signed-off-by: David Galiffi Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher Cc: Signed-off-by: Greg Kroah-Hartman

drm/amd/display: fix potential integer overflow when shifting 32 bit variable bl_pwm

2020-10-29T09:11:13+00:00

[ Upstream commit 1d5503331b12a76266049289747dfd94f1643fde ] The 32 bit unsigned integer bl_pwm is being shifted using 32 bit arithmetic and then being assigned to a 64 bit unsigned integer. There is a potential for a 32 bit overflow so cast bl_pwm to enforce a 64 bit shift operation to avoid this. Addresses-Coverity: ("unintentional integer overflow") Fixes: 3ba01817365c ("drm/amd/display: Move panel_cntl specific register from abm to panel_cntl.") Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fix incorrect backlight register offset for DCN

2020-08-10T22:08:36+00:00

[Why] Typo in backlight refactor inctroduced wrong register offset. [How] Change DCE to DCN register map for PWRSEQ_REF_DIV Cc: stable@vger.kernel.org Signed-off-by: Aric Cyr Reviewed-by: Ashley Thomas Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher

drm/amd/display: Read VBIOS Golden Settings Tbl

2020-08-06T20:47:13+00:00

[Why] For ver.4.4 and higher VBIOS contains default setting table. {How] Read Golden Settings Table from VBIOS, apply Aux tuning parameters. Signed-off-by: Igor Kravchenko Reviewed-by: Aric Cyr Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd/display: Use hw lock mgr

2020-08-06T20:42:07+00:00

[Why] Feature requires synchronization of dig, pipe, and cursor locking between driver and fw. [How] Set flag to force psr to use hw lock mgr. Signed-off-by: Wyatt Wood Reviewed-by: Anthony Koo Acked-by: Eryk Brol Signed-off-by: Alex Deucher

drm/amd/display: Initialize psr debug flags to 0

2020-07-02T16:02:52+00:00

[Why] Debug flags are not set by default. [How] Set debug flags to 0 Signed-off-by: Wyatt Wood Reviewed-by: Anthony Koo Acked-by: Eryk Brol Signed-off-by: Alex Deucher

drm/amd/display: Use dmub fw to lock pipe, cursor, dig

2020-07-01T05:59:24+00:00

[Why] Hw lock manager adds the ability to lock pipe, cursor, and dig in fw. [How] Send hw lock command to fw to lock pipe, cursor, and dig. Signed-off-by: Wyatt Wood Reviewed-by: Anthony Koo Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: label internally used symbols as static

2020-07-01T05:59:23+00:00

Used sparse(make C=1) to find these loose ends. Signed-off-by: Nirmoy Das Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/display: Passing initial SDP deadline to dmub

2020-07-01T05:59:20+00:00

[Why] The SDP deadline indicate the vertical time to send CRC infopacket in PSR. Signed-off-by: po-tchen Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher