kernel/linux.git/drivers/gpu/drm/amd/display/dc/dccg, branch linux-7.0.y

drm/amd/display: Check for S0i3 to be done before DCCG init on DCN21

2026-03-11T18:01:39+00:00

[WHY] On DCN21, dccg2_init() is called in dcn10_init_hw() before bios_golden_init(). During S0i3 resume, BIOS sets MICROSECOND_TIME_BASE_DIV to 0x00120464 as a marker. dccg2_init() overwrites this to 0x00120264, causing dcn21_s0i3_golden_init_wa() to misdetect the state and skip golden init. Eventually during the resume sequence, a flip timeout occurs. [HOW] Skip DCCG on dccg2_is_s0i3_golden_init_wa_done() on DCN21. Fixes: 4c595e75110e ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.") Reviewed-by: Aurabindo Pillai Signed-off-by: Ivan Lipski Signed-off-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher (cherry picked from commit c61eda434336cf2c033aa35efdc9a08b31d2fdfa)

drm/amd/display: Add missing DCCG register entries for DCN20-DCN316

2026-03-11T18:01:16+00:00

Commit 4c595e75110e ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.") moved register writes from hwseq to dccg2_*() functions but did not add the registers to the DCCG register list macros. The struct fields default to 0, so REG_WRITE() targets MMIO offset 0, causing a GPU hang on resume (seen on DCN21/DCN30 during IGT kms_cursor_crc@cursor-suspend). Add - MICROSECOND_TIME_BASE_DIV - MILLISECOND_TIME_BASE_DIV - DCCG_GATE_DISABLE_CNTL - DCCG_GATE_DISABLE_CNTL2 - DC_MEM_GLOBAL_PWR_REQ_CNTL to macros in dcn20_dccg.h, dcn301_dccg.h, dcn31_dccg.h, and dcn314_dccg.h. Fixes: 4c595e75110e ("drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.") Reported-by: Rafael Passos Reviewed-by: Aurabindo Pillai Signed-off-by: Ivan Lipski Signed-off-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher (cherry picked from commit e6e2b956fc814de766d3480be7018297c41d3ce0)

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-22T01:09:51+00:00

This was done entirely with mindless brute force, using git grep -l '\

treewide: Replace kmalloc with kmalloc_obj for non-scalar types

2026-02-21T09:02:28+00:00

This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook

drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.

2026-02-19T17:16:10+00:00

[Why] Direct DCCG register access in hwseq layer was creating register conflicts. [How] Migrated DCCG registers from hwseq-dccg component. Reviewed-by: Martin Leung Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Expose functions of other dcn use

2026-02-19T17:16:10+00:00

[Why & HOw] Expose some functions for later dcns to reuse Reviewed-by: Charlene Liu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dmytro Laktyushkin Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Revert "Migrate DCCG register access from hwseq to dccg component."

2026-02-12T20:14:45+00:00

[Why & How] This reverts commit 949adb4789fe3c24eea01d9c2efe94ab92694a0d, which causes regressions related to HDCP when resuming from S3. Reviewed-by: Joshua Aberback Signed-off-by: Nicholas Carbones Signed-off-by: Tom Chung Signed-off-by: Alex Deucher

drm/amd/display: Make some DCN35 DCCG symbols non-static

2026-02-03T21:39:41+00:00

In order to have few DCN35 functions be leveraged for future ASIC implementations. Expose them to the dcn35_dccg.h header. Reviewed-by: Ovidiu Bunea Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Migrate DCCG register access from hwseq to dccg component.

2026-02-03T21:39:09+00:00

[why] Direct DCCG register access in hwseq layer was creating register conflicts. [how] Migrated DCCG registers from hwseq to dccg component. Reviewed-by: Martin Leung Signed-off-by: Bhuvanachandra Pinninti Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add more DC HW state info to underflow logging

2025-10-28T13:57:44+00:00

[Why] Debugging underflow issues frequently requires knowing the HW state at the time of underflow. To enable capturing this HW state information, interface functions are needed for the various DC HW blocks. [How] This change adds the interface functions to read HW state for the following DC HW blocks: - HUBBUB - HUBP - DPP - MPC - OPP - DSC - OPTC - DCCG Reviewed-by: George Shen Signed-off-by: Karen Chen Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher