kernel/linux.git/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c, branch v6.3

drm/amd/display: remove outdated 8bpc comments

2023-03-23T13:34:07+00:00

[Why] The commit c76e483cd916 ("drm/amd/display: Don't restrict bpc to 8 bpc") removes the historical 8bpc dependency and sets max_bpc to 16. [How] The comment that states "8bpc for non-edp" needs to be removed as well. Reviewed-by: Harry Wentland Acked-by: Qingqing Zhuo Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Write to correct dirty_rect

2023-03-14T14:40:02+00:00

When FB_DAMAGE_CLIPS are provided in a non-MPO scenario, the loop does not use the counter i. This causes the fill_dc_dity_rect() to always fill dirty_rects[0], causing graphical artifacts when a damage clip aware DRM client sends more than 1 damage clip. Instead, use the flip_addrs->dirty_rect_count which is incremented by fill_dc_dirty_rect() on a successful fill. Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2453 Signed-off-by: Benjamin Cheng Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.1.x

drm/amd/display: Ext displays with dock can't recognized after resume

2023-03-02T03:42:53+00:00

[Why] Needs to set the default value of the LTTPR timeout after resume. [How] Set the default (3.2ms) timeout at resuming if the sink supports LTTPR Reviewed-by: Jerry Zuo Acked-by: Qingqing Zhuo Signed-off-by: Ryan Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: fix dm irq error message in gpu recover

2023-03-02T03:39:50+00:00

[Why] Variable adev->crtc_irq.num_types was initialized as the value of adev->mode_info.num_crtc at early_init stage, later at hw_init stage, the num_crtc changed due to the display pipe harvest on some SKUs, but the num_types was not updated accordingly, that cause below error in gpu recover. *ERROR* amdgpu_dm_set_crtc_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_crtc_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_crtc_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_pflip_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_pflip_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_pflip_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_pflip_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_vupdate_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_vupdate_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_vupdate_irq_state: crtc is NULL at id :3 [How] Defer the initialization of num_types to eliminate the error logs. Signed-off-by: tiancyin Reviewed-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Don't restrict bpc to 8 bpc

2023-03-02T03:38:06+00:00

This will let us pass the kms_hdr.bpc_switch IGT test. The reason the bpc restriction was required is historical. At one point in time we were not falling back to a lower bpc when we didn't have enough bandwidth for the maximum bpc reported by a display. This meant that we couldn't enable some high refresh modes unless we limitted the bpc. Starting with this patch the issue is fixed: commit cbd14ae7ea93 ("drm/amd/display: Fix incorrectly pruned modes with deep color") This patch implemented a fallback mechanism if mode validation failed at the max bpc. This means users now automatically get all modes that can be supported by at least 6 bpc. The driver will enable the mode with the highest possible bpc that is supported by the display. v2: - explain why this is no longer needed (Michel) - refer to commit that fixed bpc fallback (Michel) Signed-off-by: Harry Wentland Cc: Pekka Paalanen Cc: Sebastian Wick Cc: Vitaly.Prosyak@amd.com Cc: Joshua Ashton Cc: dri-devel@lists.freedesktop.org Cc: amd-gfx@lists.freedesktop.org Cc: Michel Dänzer Reviewed-by: Joshua Ashton Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher

drm/amd/display: disable SubVP + DRR to prevent underflow

2023-02-16T03:26:22+00:00

[Why&How] Temporarily disable SubVP+DRR since Xorg has an architectural limitation where freesync will not work in a multi monitor configuration. SubVP+DRR requires that freesync be working. Whether OS has variable refresh setting enabled or not, the state on the crtc remains same unless an application requests VRR. Due to this, there is no way to know whether freesync will actually work or not while we are on the desktop from the kernel's perspective. If userspace does not have a limitation with multi-display freesync (for example wayland), then this feature can be enabled by adding a dcfeaturemask option to amdgpu on the kernel cmdline like: amdgpu.dcfeaturemask=0x200 Signed-off-by: Aurabindo Pillai Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: Fail atomic_check early on normalize_zpos error

2023-02-16T03:25:04+00:00

[Why] drm_atomic_normalize_zpos() can return an error code when there's modeset lock contention. This was being ignored. [How] Bail out of atomic check if normalize_zpos() returns an error. Fixes: b261509952bc ("drm/amd/display: Fix double cursor on non-video RGB MPO") Signed-off-by: Leo Li Tested-by: Mikhail Gavrilov Reviewed-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Add support for multiple overlay planes

2023-02-14T21:06:38+00:00

[Why] We only allowed 1 overlay plane. But now some ASICS can support multiple overlay planes. [How] Use max_slave_planes as the number of overlays we can support. Also since we cannot draw cursor over a video plane, we need to make sure that we reject commits where the topmost plane is a video plane (overlay only). Reviewed-by: Nicholas Kazlauskas Acked-by: Qingqing Zhuo Signed-off-by: Bhawanpreet Lakha Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix video glitch while drag window in PSR-SU

2023-02-14T21:04:17+00:00

[Why] Dmub will cache the video position data during PSR-SU enable. The dmub will use an outdated MPO video position if user try to drag the video window and it will cause video glitch. [How] Disable the PSR-SU temporarily while user drag the video window. The PSR-SU will be re-enabled after the video window is stable. Reviewed-by: Sun peng Li Acked-by: Qingqing Zhuo Signed-off-by: Tom Chung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Extract temp drm mst deallocation wa into its own function

2023-02-14T21:03:35+00:00

[why] A recent change was made to implement temporary workaround due DRM update in MST interfaces. The workaround is added into our generic deallocation MST sequence. This ticket is to extract this temporary workaround into its own function so it is differentiated from our generic sequence. Reviewed-by: Jerry Zuo Acked-by: Qingqing Zhuo Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher