<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/soc21.c, branch linux-7.1.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.1.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.1.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-03-02T21:46:34+00:00</updated>
<entry>
<title>drm/amdgpu: Add pcie64 indirect to register block</title>
<updated>2026-03-02T21:46:34+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-12-09T05:41:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=74b9c49e6d8ba2586081aecd86af96c510092103'/>
<id>urn:sha1:74b9c49e6d8ba2586081aecd86af96c510092103</id>
<content type='text'>
Move 64-bit pcie indirect read/writes to register access block.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add pcie indirect to register block</title>
<updated>2026-03-02T21:46:28+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-12-09T04:17:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e84d7e717bf94bd977e20e5ca52d0b2ae4e19802'/>
<id>urn:sha1:e84d7e717bf94bd977e20e5ca52d0b2ae4e19802</id>
<content type='text'>
Move pcie indirect access to register access block.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add pciep method to register block</title>
<updated>2026-03-02T21:46:19+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-12-09T04:05:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5d82f451b0ab2d7137d9ffdd0d15675b756ab29d'/>
<id>urn:sha1:5d82f451b0ab2d7137d9ffdd0d15675b756ab29d</id>
<content type='text'>
Move pcie port method to register access block.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add didt method to register block</title>
<updated>2026-03-02T21:46:03+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-12-08T13:22:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4780a26a96f88631d56f7bd0eee4e2c6721a279b'/>
<id>urn:sha1:4780a26a96f88631d56f7bd0eee4e2c6721a279b</id>
<content type='text'>
Move didt callbacks to register access block.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add uvd indirect to register block</title>
<updated>2026-03-02T21:43:10+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-12-08T13:08:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=366201e790f10ddc081ef787e2e345553b87459d'/>
<id>urn:sha1:366201e790f10ddc081ef787e2e345553b87459d</id>
<content type='text'>
Add uvd indirect method to register access block and replace the
existing calls from adev.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add smc method to register block</title>
<updated>2026-03-02T21:42:38+00:00</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-12-08T12:56:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f4eb08f8b216c334752246fe24e1304477d78968'/>
<id>urn:sha1:f4eb08f8b216c334752246fe24e1304477d78968</id>
<content type='text'>
Define register access block which consolidates different register access
methods. Add smc method to register access block.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable DPG support for VCN5</title>
<updated>2026-03-02T21:35:17+00:00</updated>
<author>
<name>sguttula</name>
<email>suresh.guttula@amd.com</email>
</author>
<published>2026-02-21T05:17:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a503c266d70d3363ba6bffb883cd6ecdb092670c'/>
<id>urn:sha1:a503c266d70d3363ba6bffb883cd6ecdb092670c</id>
<content type='text'>
This will set DPG flags for enabling power gating on GFX11_5_4

Signed-off-by: sguttula &lt;suresh.guttula@amd.com&gt;
Reviewed-by: Pratik Vishwakarma &lt;Pratik.Vishwakarma@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Add CG/PG flags for GC 11.5.4</title>
<updated>2026-02-12T20:21:30+00:00</updated>
<author>
<name>Pratik Vishwakarma</name>
<email>Pratik.Vishwakarma@amd.com</email>
</author>
<published>2026-01-28T10:12:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=33ed922d24d0c73bdb51b2ddf8f2de8b42ffb015'/>
<id>urn:sha1:33ed922d24d0c73bdb51b2ddf8f2de8b42ffb015</id>
<content type='text'>
Enable GFXOff for GC 11.5.4

Signed-off-by: Pratik Vishwakarma &lt;Pratik.Vishwakarma@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable mode2 reset for SMU IP v15.0.0</title>
<updated>2026-02-12T20:21:25+00:00</updated>
<author>
<name>Pratik Vishwakarma</name>
<email>Pratik.Vishwakarma@amd.com</email>
</author>
<published>2026-01-28T10:10:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=39a96f126d43e504be54230ff13834277b543802'/>
<id>urn:sha1:39a96f126d43e504be54230ff13834277b543802</id>
<content type='text'>
Set the default reset method to mode2 for SMU 15.0.0.

Signed-off-by: Kanala Ramalingeswara Reddy &lt;Kanala.RamalingeswaraReddy@amd.com&gt;
Signed-off-by: Pratik Vishwakarma &lt;Pratik.Vishwakarma@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/soc21: fix xclk for APUs</title>
<updated>2026-01-28T21:21:31+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2026-01-16T22:33:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=637fee3954d4bd509ea9d95ad1780fc174489860'/>
<id>urn:sha1:637fee3954d4bd509ea9d95ad1780fc174489860</id>
<content type='text'>
The reference clock is supposed to be 100Mhz, but it
appears to actually be slightly lower (99.81Mhz).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14451
Reviewed-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
