kernel/linux.git/drivers/gpu/drm/amd/amdgpu/soc15_common.h, branch v6.3

drm/amdgpu: add new write field for soc21

2022-04-28T21:48:35+00:00

add new write field macro to handle soc21 registers with reg prefix Acked-by: Christian König Signed-off-by: Stanley.Yang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: switch to amdgpu_sriov_rreg/wreg

2022-01-25T23:00:33+00:00

Instead of ip specific implementation for rlcg indirect register access Signed-off-by: Hawking Zhang Reviewed-by: Zhou, Peng Ju Acked-by: Christian König Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitions

2021-12-28T21:01:55+00:00

Add helper macros to change register access from direct to indirect. Signed-off-by: Victor Skvortsov Reviewed-by: David Nieto Signed-off-by: Alex Deucher

drm/amdgpu: Change the imprecise function name

2021-07-23T14:07:59+00:00

The callback functions are used for SRIOV read/write instead of just for rlcg read/write Signed-off-by: Roy Sun Reviewed-by: Zhou pengju Signed-off-by: Alex Deucher

drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10

2021-06-07T18:57:38+00:00

The NV12 and VEGA10 share the same interface W/RREG32_SOC15*, the callback functions in these macros may not be defined, so NULL pointer must be checked but not in macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check. Signed-off-by: Peng Ju Zhou Reviewed-by: Emily Deng Signed-off-by: Alex Deucher

drm/amdgpu: soc15 register access through RLC should only apply to sriov runtime

2021-06-04T16:40:00+00:00

On SRIOV, driver should only access register through RLC in runtime Acked-by: Alex Deucher Signed-off-by: shaoyunl Signed-off-by: Alex Deucher

drm/amdgpu: Indirect register access for Navi12 sriov

2021-05-21T14:32:06+00:00

This patch series are used for GC/MMHUB(part)/IH_RB_CNTL indirect access in the SRIOV environment. There are 4 bits, controlled by host, to control if GC/MMHUB(part)/IH_RB_CNTL indirect access enabled. (one bit is master bit controls other 3 bits) For GC registers, changing all the register access from MMIO to RLC and use RLC as the default access method in the full access time. For partial MMHUB registers, changing their access from MMIO to RLC in the full access time, the remaining registers keep the original access method. For IH_RB_CNTL register, changing it's access from MMIO to PSP. Signed-off-by: Peng Ju Zhou Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: indirect register access for nv12 sriov

2021-04-09T20:50:17+00:00

1. expand rlcg interface for gc & mmhub indirect access 2. add rlcg interface for no kiq v2: squash in fix for gfx9 (Changfeng) Signed-off-by: Peng Ju Zhou Reviewed-by: Emily.Deng Signed-off-by: Alex Deucher

drm/amdgpu: enable watchdog feature for SQ of aldebaran

2021-03-24T02:59:52+00:00

SQ's watchdog timer monitors forward progress, a mask of which waves caused the watchdog timeout is recorded into ras status registers and then trigger a system fatal error event. v2: 1. change *query_timeout_status to *query_sq_timeout_status. 2. move query_sq_timeout_status into amdgpu_ras_do_recovery. 3. add module parameters to enable/disable fatal error event and modify the watchdog timer. v3: 1. remove unused parameters of *enable_watchdog_timer Signed-off-by: Dennis Li Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: add ras support for gfx of aldebaran

2021-03-24T02:59:48+00:00

add edc counter/status reset and query functions for gfx block of aldebaran. v2: change to clear edc counter explicitly aldebaran hardware will not clear edc counter after driver reading them, so driver should clear them explicitly. Signed-off-by: Dennis Li Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher