kernel/linux.git/drivers/gpu/drm/amd/amdgpu/soc15_common.h, branch linux-7.0.yLinux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y2023-11-09T22:03:16+00:00drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2)2023-11-09T22:03:16+00:00Victor Luvictorchengchi.lu@amd.com2023-08-08T18:28:56+00:00urn:sha1:197264284303b30b26e885d83680f594e69840e5
W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC
should be used instead when inst != 0.
v2: rebase
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add pcs xgmi v6.4.0 ras support2023-11-09T22:02:20+00:00Yang Wangkevinyang.wang@amd.com2023-11-03T09:00:10+00:00urn:sha1:27d80f7d68185a62e101575d302539353622e523
add pcs xgmi v6.4.0 ras support
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add xcc param to SRIOV kiq write and WREG32_SOC15_IP_NO_KIQ (v4)2023-11-09T22:01:10+00:00Victor Luvictorchengchi.lu@amd.com2023-08-08T17:57:16+00:00urn:sha1:bc3c566071c8504f5d7c73a4171ead394f097639
WREG32/RREG32_SOC15_IP_NO_KIQ and amdgpu_virt_kiq_reg_write_reg_wait
are not using the correct rlcg interface or mec engine, respectively.
Add xcc instance parameter to them.
v4: Use GET_INST and squash commit with:
"drm/amdgpu: Add xcc_inst param to amdgpu_virt_kiq_reg_write_reg_wait"
v3: xcc not needed for MMMHUB
v2: rebase
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)2023-07-18T15:16:41+00:00Victor Luvictorchengchi.lu@amd.com2023-06-16T15:01:59+00:00urn:sha1:8ed49dd1d3a7448744d57e1da2062b074cba2e49
Add RLCG interface support for gfx v9.4.3 and multiple XCCs.
Do not enable it yet.
v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs
in amdgpu_mm_wreg_mmio_rlc
v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Zhigang Luo <zhigang.luo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: convert logical instance mask to physical one2023-06-09T14:37:08+00:00Tao Zhoutao.zhou1@amd.com2023-02-27T08:31:56+00:00urn:sha1:af2ba368838ee4913e758f34e3d8bbfeb110be36
Convert instance mask for the convenience of RAS TA.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fixes a JPEG get write/read pointer bug2023-06-09T13:56:19+00:00Sonny Jiangsonjiang@amd.com2023-03-22T19:49:29+00:00urn:sha1:55ff23d9eb814dce8393a4c471259ded5a85d461
Need parentheses for the micro parameters.
Signed-off-by: Sonny Jiang <sonjiang@amd.com>
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add helpers to access registers on different AIDs2023-06-09T13:48:05+00:00Le Male.ma@amd.com2022-09-27T09:51:33+00:00urn:sha1:2fa480d36eb302712e48dce4d2f6564b24426be3
SMN address which is larger than 32bit has different indications
through bit[34:32] on different AIDs.
v2: put smn addressing of different AIDs into asic specific place
v3: change to ext_id/ext_offset naming
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Use instance lookup table for GC 9.4.32023-06-09T13:45:44+00:00Lijo Lazarlijo.lazar@amd.com2022-07-05T04:26:41+00:00urn:sha1:659a4ab8e27eb39cc61cb74cc714ba1a8f8c9a61
Register accesses need to be based on physical instance on bare metal.
Pass the right instance using logical to physical instance lookup
table before accessing registers. Add a macro GET_INST to get the right
physical instance of an IP corresponding to a logical instance.
v2: fix gfx_v9_4_3_check_rlcg_range() (Alex)
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/: add more macro to support offset variant2023-06-09T13:40:46+00:00James ZhuJames.Zhu@amd.com2022-01-20T03:32:41+00:00urn:sha1:81283fee15ea6afb1e32defb369c3b96d2d6765c
Add more macro to support offset variant and
simplify macro SOC15_WAIT_ON_RREG.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: make the WREG32_SOC15_xx macro to support multi GC2023-06-09T13:40:29+00:00Shiwu Zhangshiwu.zhang@amd.com2021-11-29T12:44:05+00:00urn:sha1:99951878b048e39278bb05d96831353eca23b75f
To write regs on different GCDs, use the inst index.
Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>