kernel/linux.git/drivers/gpu/drm/amd/amdgpu/soc15.h, branch linux-6.9.yLinux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=linux-6.9.y2023-11-29T21:49:35+00:00drm/amdgpu: Read aquavanjaram PCIE register state2023-11-29T21:49:35+00:00Lijo Lazarlijo.lazar@amd.com2023-10-06T08:50:45+00:00urn:sha1:081a6eda2b25092e1466f09eb46d829488b75730
Add support to read aqua vanjaram PCIE register state
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add soc config init for GC9.4.3 ASICs2023-06-09T13:49:39+00:00Lijo Lazarlijo.lazar@amd.com2022-09-23T09:13:17+00:00urn:sha1:e56c9ef6cb35f33dc83f635419ae55adf69db9fc
Add function to initialize soc configuration information for GC 9.4.3
ASICs. Use it to map IPs and other SOC related information once IP
configuration information is available through discovery.
For GC9.4.3 compute partition related callbacks are initialized as part
of configuration init.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add helpers to access registers on different AIDs2023-06-09T13:48:05+00:00Le Male.ma@amd.com2022-09-27T09:51:33+00:00urn:sha1:2fa480d36eb302712e48dce4d2f6564b24426be3
SMN address which is larger than 32bit has different indications
through bit[34:32] on different AIDs.
v2: put smn addressing of different AIDs into asic specific place
v3: change to ext_id/ext_offset naming
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: switch to aqua_vanjaram_doorbell_index_init2023-06-09T13:47:35+00:00Le Male.ma@amd.com2022-05-24T11:44:27+00:00urn:sha1:1dfcdc30270a80ba5b45f922833c0c0e56d82576
New doorbell index assignment is used by aqua_vanjaram.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add IP instance map for aqua vanjaram2023-06-09T13:47:23+00:00Lijo Lazarlijo.lazar@amd.com2022-06-29T10:15:06+00:00urn:sha1:cab7d478da112e66f2ad8eec7dcfc0aa2a5babe1
Add XCC logical to physical instance map for aqua vanjaram
v2:
Keep look up table only for required IPs, for others return
default mapping (Felix).
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add xcc index argument to soc15_grbm_select2023-04-18T20:28:55+00:00Le Male.ma@amd.com2021-11-17T08:28:51+00:00urn:sha1:5aa998baab3360d0f1b93d6aff3df924045f956c
To support grbm select for multiple XCD case.
v2: unify naming style
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: drop soc15_set_ip_blocks()2021-10-20T15:43:57+00:00Alex Deucheralexander.deucher@amd.com2021-10-11T13:44:47+00:00urn:sha1:7092432e3cb1a47f1ba7fe59ceb23f85bd8e09a4
No longer used since IP enumeration is now driven by
amdgpu IP discovery code.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/soc15: export common IP functions2021-10-04T19:22:59+00:00Alex Deucheralexander.deucher@amd.com2021-07-30T18:50:07+00:00urn:sha1:994470b252dcc0a430da866a17753b5ca3f5cd34
So they can be driven by IP discovery table.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: make soc15_common_ip_funcs static2021-09-23T20:35:27+00:00Alex Deucheralexander.deucher@amd.com2021-07-30T18:46:53+00:00urn:sha1:2485e2753ec896b169526e3ef7988589d1c458f5
It's not used outside of soc15.c
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: refine ras codes for GC utc of aldebaran2021-03-24T02:59:50+00:00Dennis LiDennis.Li@amd.com2021-01-27T06:36:15+00:00urn:sha1:4abc2567f0ebf1c7113430e25ee960408f5ebcb1
The bank number of both VML2 and ATCL2 are changed to 8, so refine
related codes to avoid defining long name arrays.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>