kernel/linux.git/drivers/gpu/drm/amd/amdgpu/sid.h, branch v6.12.80

drm/amdgpu: Clean up KFD VMID assignment

2020-07-02T16:02:50+00:00

The KFD VMID assignment was hard-coded in a few places. Consolidate that in a single variable adev->vm_manager.first_kfd_vmid. The value is still assigned in gmc-ip-version-specific code. Signed-off-by: Felix Kuehling Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: SI support for VCE clock control

2020-07-02T16:02:49+00:00

Port functionality from the Radeon driver to support VCE clock control. Signed-off-by: Alex Jivin Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: SI support for UVD clock control

2020-07-02T16:02:49+00:00

Port functionality from the Radeon driver to support UVD clock control. Signed-off-by: Alex Jivin Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher

drm amdgpu: SI UVD PACKET_TYPE0

2020-07-01T05:59:24+00:00

Fix packet_type0 definition in sid. Signed-off-by: Sonny Jiang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu/uvd3.x: fix register definition warnings

2020-07-01T05:59:24+00:00

drop the duplicate register macros from sid.h and use the standard ones in the oss register headers. Acked-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: enable ABGR and XBGR formats (v2)

2018-08-27T16:10:19+00:00

Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled (v2) Crossbar registers are defined and used to swap red and blue channels, keeping the existing coding style in each of the dce modules. After setting crossbar bits in fb_swap, use bitwise OR for big endian where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD() Signed-off-by: Mauro Rossi Signed-off-by: Alex Deucher

drm/amdgpu: move misc si headers into amdgpu

2017-01-27T17:20:41+00:00

Move these to the amdgpu directory to match what we do for other asics. Acked-by: Christian König Signed-off-by: Alex Deucher