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<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/si.h, branch v6.12.80</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2018-02-19T19:18:08+00:00</updated>
<entry>
<title>drm/amdgpu: implement gmc_v6_0_emit_flush_gpu_tlb</title>
<updated>2018-02-19T19:18:08+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-01-12T15:58:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4fef88bd002985908064ea6760623f09ac44355b'/>
<id>urn:sha1:4fef88bd002985908064ea6760623f09ac44355b</id>
<content type='text'>
Unify tlb flushing for gmc v6.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rework IP block registration (v2)</title>
<updated>2016-10-25T18:38:45+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-10-13T21:41:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a12551072126758ecb0743147054f22bf233bb7d'/>
<id>urn:sha1:a12551072126758ecb0743147054f22bf233bb7d</id>
<content type='text'>
This makes it easier to replace specific IP blocks on
asics for handling virtual_dce, DAL, etc. and for building
IP lists for hw or tables.  This also stored the status
information in the same structure.

v2: split out spelling fix into a separate patch
    add a function to add IPs to the list

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add si implementation v10</title>
<updated>2016-08-31T16:11:19+00:00</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T06:08:49+00:00</published>
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<id>urn:sha1:62a37553414a344491c64e8fd89577dcc1b8bcbb</id>
<content type='text'>
v5: rebase fixes
v6: add mgcg arrays
v7: rebase fixes
v8: rebase fixes
v9: add get_disabled_bios(), make get_xclk static
v10: fix oland and hainan asic specific handle at si_program_aspm

Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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