kernel/linux.git/drivers/gpu/drm/amd/amdgpu/si.c, branch v7.1-rc6Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v7.1-rc62026-03-02T21:46:41+00:00drm/amdgpu: Move pcie lock to register block2026-03-02T21:46:41+00:00Lijo Lazarlijo.lazar@amd.com2025-12-09T06:02:42+00:00urn:sha1:b2d55124712b3551842bab228f27db3df8068b30
Move pcie register access lock to register access block.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add pcie indirect to register block2026-03-02T21:46:28+00:00Lijo Lazarlijo.lazar@amd.com2025-12-09T04:17:13+00:00urn:sha1:e84d7e717bf94bd977e20e5ca52d0b2ae4e19802
Move pcie indirect access to register access block.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add pciep method to register block2026-03-02T21:46:19+00:00Lijo Lazarlijo.lazar@amd.com2025-12-09T04:05:18+00:00urn:sha1:5d82f451b0ab2d7137d9ffdd0d15675b756ab29d
Move pcie port method to register access block.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add didt method to register block2026-03-02T21:46:03+00:00Lijo Lazarlijo.lazar@amd.com2025-12-08T13:22:42+00:00urn:sha1:4780a26a96f88631d56f7bd0eee4e2c6721a279b
Move didt callbacks to register access block.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add uvd indirect to register block2026-03-02T21:43:10+00:00Lijo Lazarlijo.lazar@amd.com2025-12-08T13:08:52+00:00urn:sha1:366201e790f10ddc081ef787e2e345553b87459d
Add uvd indirect method to register access block and replace the
existing calls from adev.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add smc method to register block2026-03-02T21:42:38+00:00Lijo Lazarlijo.lazar@amd.com2025-12-08T12:56:09+00:00urn:sha1:f4eb08f8b216c334752246fe24e1304477d78968
Define register access block which consolidates different register access
methods. Add smc method to register access block.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Convert DRM_*() to drm_*()2026-01-05T21:59:55+00:00Mario Limonciello (AMD)superm1@kernel.org2025-12-15T01:12:27+00:00urn:sha1:e291729873095262697758c389c8d7affa81bdcc
The drm_*() macros include the device which is helpful for debugging
issues in multi-GPU systems.
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Make pre_asic_init optional2025-12-08T18:56:42+00:00Lijo Lazarlijo.lazar@amd.com2025-11-28T07:06:46+00:00urn:sha1:018fd6d7d92d704709e8dfe497fe3aac1566e90f
pre_asic_init is not required for all SOCs. Make it optional and remove
empty implementations.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/vce1: Workaround PLL timeout on FirePro W90002025-11-12T02:54:19+00:00Timur Kristóftimur.kristof@gmail.com2025-11-07T15:57:45+00:00urn:sha1:baefc7cdac82e39fac31818ecc799a6b9b14a312
Sometimes the VCE PLL times out waiting for CTLACK/CTLACK2.
When it happens, the VCE still works, but much slower.
Observed on a Tahiti GPU, but not all:
- FirePro W9000 has the issue
- Radeon R9 280X not affected
- Radeon HD 7990 not affected
As a workaround, on the affected chip just don't put the
VCE PLL in sleep mode. Leaving the VCE PLL in bypass mode
or reset mode both work. Using bypass mode is simpler.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/vce1: Enable VCE1 on Tahiti, Pitcairn, Cape Verde GPUs2025-11-12T02:54:18+00:00Timur Kristóftimur.kristof@gmail.com2025-11-07T15:57:44+00:00urn:sha1:eabc71661f01c74e5da3182b268170626e8bd290
Add the VCE1 IP block to the SI GPUs that have it.
Advertise the encoder capabilities corresponding to VCE1,
so the userspace applications can detect and use it.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Co-developed-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>