Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80 2024-04-26T21:22:39+00:00 2024-04-26T21:22:39+00:00 Sunil Khatri sunil.khatri@amd.com 2024-04-16T11:00:50+00:00 urn:sha1:40356542c36160bddee9fdf25b9248e0c9e6503b Add the protoype for print ip state to be used to print the registers in devcoredump during a gpu reset. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-04-26T21:22:39+00:00 Sunil Khatri sunil.khatri@amd.com 2024-04-01T10:28:38+00:00 urn:sha1:e21d253bd74bd422347d202ea2205cdc7623eed2 Add the prototype to dump ip registers for all ips of different asics and set them to NULL for now. Based on the requirement add a function pointer for each of them. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-04-10T02:07:59+00:00 Ma Jun Jun.Ma2@amd.com 2024-03-27T09:26:08+00:00 urn:sha1:b2207dc6989f5c913cca932eb8720b6ad0725d67 Add support for MACO flag checking. MACO mode only works if BACO is supported. Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-02-22T17:05:20+00:00 Ilpo Järvinen ilpo.jarvinen@linux.intel.com 2024-02-15T13:31:54+00:00 urn:sha1:bb87e511b21bbe071d712ebbd02efe31023023fc Convert open coded RMW accesses for LNKCTL2 to use pcie_capability_clear_and_set_word() which makes its easier to understand what the code tries to do. LNKCTL2 is not really owned by any driver because it is a collection of control bits that PCI core might need to touch. RMW accessors already have support for proper locking for a selected set of registers (LNKCTL2 is not yet among them but likely will be in the future) to avoid losing concurrent updates. Acked-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2023-10-26T22:41:23+00:00 Mario Limonciello mario.limonciello@amd.com 2023-10-23T20:47:43+00:00 urn:sha1:1a6513de493d13f8d7501611fcc5bbaea4c799b3 There is no need for every ASIC driver to perform the same check. Move the duplicated code into amdgpu_device_should_use_aspm(). Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2023-08-21T19:11:35+00:00 Ilpo Järvinen ilpo.jarvinen@linux.intel.com 2023-07-17T12:04:57+00:00 urn:sha1:ce7d88110b9ed5f33fe79ea6d4ed049fb0e57bce Don't assume that only the driver would be accessing LNKCTL. ASPM policy changes can trigger write to LNKCTL outside of driver's control. And in the case of upstream bridge, the driver does not even own the device it's changing the registers for. Use RMW capability accessors which do proper locking to avoid losing concurrent updates to the register value. Suggested-by: Lukas Wunner <lukas@wunner.de> Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts") Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Link: https://lore.kernel.org/r/20230717120503.15276-6-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> 2023-04-18T20:28:55+00:00 Le Ma le.ma@amd.com 2022-05-24T03:22:49+00:00 urn:sha1:d51ac6d0a23caf1005cb640f8533161c5d2dd0c0 v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-02-17T20:59:05+00:00 Mario Limonciello mario.limonciello@amd.com 2022-02-17T05:19:58+00:00 urn:sha1:0ab5d711ec74d9e60673900974806b7688857947 Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-08-06T01:17:58+00:00 Ryan Taylor Ryan.Taylor@amd.com 2021-06-18T20:16:37+00:00 urn:sha1:733ee71ae0d03a8b03711dca8bc94c8ac05a6bc3 Move dce_virtual into amdgpu_vkms and update all references to dce_virtual with amdgpu_vkms. v2: Removed more references to dce_virtual. v3: Restored display modes from previous implementation. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reported-by: kernel test robot <lkp@intel.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-02-26T22:23:49+00:00 Alex Deucher alexander.deucher@amd.com 2021-02-02T16:11:45+00:00 urn:sha1:6f786950b1ff051c6dd913b1bb3aaa9b57befcbf And just use the ioctl index. They are the same. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>