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<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c, branch v6.18.15</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.18.15</id>
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<updated>2026-02-26T22:59:42+00:00</updated>
<entry>
<title>drm/amdgpu: move reset debug disable handling</title>
<updated>2026-02-26T22:59:42+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-10-14T21:01:05+00:00</published>
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<id>urn:sha1:3759040d6d7c1f8f4144bd52357d3220b3972684</id>
<content type='text'>
[ Upstream commit ad0a48e531a3137cec16bb5f8f60c8cc8de06b01 ]

Move everything to the supported resets masks rather than
having an explicit misc checks for this.

Reviewed-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Stable-dep-of: 46a2cb7d24f2 ("drm/amdgpu/sdma5: enable queue resets unconditionally")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Update SDMA firmware version check for user queue support</title>
<updated>2025-08-04T19:48:14+00:00</updated>
<author>
<name>Jesse.Zhang</name>
<email>Jesse.Zhang@amd.com</email>
</author>
<published>2025-08-04T00:43:15+00:00</published>
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<id>urn:sha1:124ffa2970087f3b9033a00a4855748514225b9d</id>
<content type='text'>
This commit fixes a firmware version check for enabling user queue
support in SDMA v7.0. The previous version check (7836028) was
incorrect and could lead to issues with PROTECTED_FENCE_SIGNAL
commands causing register conflicts between MCU_DBG0 and MCU_DBG1.

Fixes: 8c011408ed84 ("drm/amdgpu/sdma7: add ucode version checks for userq support")
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 92e2449241516c95aab95eea91faecd0fa2b7ed5)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: move reset support type checks into the caller</title>
<updated>2025-07-17T16:36:56+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-07-15T15:55:05+00:00</published>
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<id>urn:sha1:6ac55eab4fc41e0ea80f9064945e4340f13d8b5c</id>
<content type='text'>
Rather than checking in the callbacks, check if the reset
type is supported in the caller.

Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/sdma7: re-emit unprocessed state on ring reset</title>
<updated>2025-07-17T16:36:54+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-05-29T17:12:35+00:00</published>
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<id>urn:sha1:ea2791d05a2e8bd483df48f548e0293edc3bcc0f</id>
<content type='text'>
Re-emit the unprocessed state after resetting the queue.

Reviewed-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: clean up sdma reset functions</title>
<updated>2025-07-16T20:08:05+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-07-07T14:22:59+00:00</published>
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<id>urn:sha1:d18e1faef6baab417cff8f6704c6279ba8f4922f</id>
<content type='text'>
Make them consistent and drop unneeded extra variables.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move scheduler wqueue handling into callbacks</title>
<updated>2025-06-30T15:58:22+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-06-16T21:45:05+00:00</published>
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<id>urn:sha1:38b20968f3d8a603a979ac50ff6cf3553e0b3daf</id>
<content type='text'>
Move the scheduler wqueue stopping and starting into
the ring reset callbacks.  On some IPs we have to reset
an engine which may have multiple queues.  Move the wqueue
handling into the backend so we can handle them as needed
based on the type of reset available.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move force completion into ring resets</title>
<updated>2025-06-30T15:57:29+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-05-29T16:58:53+00:00</published>
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<id>urn:sha1:2dee58ca471dae05c473270d0fb74efe01a78ccb</id>
<content type='text'>
Move the force completion handling into each ring
reset function so that each engine can determine
whether or not it needs to force completion on the
jobs in the ring.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update ring reset function signature</title>
<updated>2025-06-30T15:57:16+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-06-05T20:12:08+00:00</published>
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<id>urn:sha1:787e2ce10fdce2b95a9ad81cc244ef22b0c200fe</id>
<content type='text'>
Going forward, we'll need more than just the vmid.  Add the
guilty amdgpu_fence.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/sdma7: add ucode version checks for userq support</title>
<updated>2025-06-24T14:04:30+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-06-20T15:39:22+00:00</published>
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<id>urn:sha1:8c011408ed842dfccdd50a90a9cf6bccdb85cc0e</id>
<content type='text'>
SDMA 7.0.0/1: 7836028

Reviewed-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add userq fence support to SDMAv7.0</title>
<updated>2025-06-03T19:32:50+00:00</updated>
<author>
<name>Arunpravin Paneer Selvam</name>
<email>Arunpravin.PaneerSelvam@amd.com</email>
</author>
<published>2025-05-27T13:43:20+00:00</published>
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<id>urn:sha1:e34bcf1594b59f9f63c084bf0646b19edf581adc</id>
<content type='text'>
- Add userq fence support to SDMAv7.0.
- GFX12's user fence irq src id differs from GFX11's,
  hence we need create a new irq srcid header file for GFX12.

  User fence irq src id information-
  GFX11 and SDMA6.0 - 0x43
  GFX12 and SDMA7.0 - 0x46

Signed-off-by: Arunpravin Paneer Selvam &lt;Arunpravin.PaneerSelvam@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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