<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/nv.h, branch v5.12.1</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v5.12.1</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v5.12.1'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2020-10-12T18:00:20+00:00</updated>
<entry>
<title>drm/amdgpu: initialize IP offset for dimgrey_cavefish</title>
<updated>2020-10-12T18:00:20+00:00</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2020-10-02T15:34:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=038d757b95f51dd59ae8852c981971cb48e8df0b'/>
<id>urn:sha1:038d757b95f51dd59ae8852c981971cb48e8df0b</id>
<content type='text'>
Add ip offset definition for dimgrey_cavefish and initialize it.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Jiansong Chen &lt;Jiansong.Chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add vangogh_reg_base_init function for van gogh</title>
<updated>2020-10-05T19:14:02+00:00</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2020-08-27T14:44:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1f9dab43c2cc19e69e368541ab8959859676e543'/>
<id>urn:sha1:1f9dab43c2cc19e69e368541ab8959859676e543</id>
<content type='text'>
This patch adds vangogh_reg_base_init function to init the register base for
van gogh.

v2: make vangogh_reg_base_init void, align equality sign

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: request init data in virt detection</title>
<updated>2020-07-02T16:02:50+00:00</updated>
<author>
<name>Wenhui Sheng</name>
<email>Wenhui.Sheng@amd.com</email>
</author>
<published>2020-06-23T03:35:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c1299461b7d68eed457478ddf3e93bbd89e5c3ca'/>
<id>urn:sha1:c1299461b7d68eed457478ddf3e93bbd89e5c3ca</id>
<content type='text'>
Move request init data to virt detection func, so we
can insert request full access between request init data
and set ip blocks.

Signed-off-by: Wenhui Sheng &lt;Wenhui.Sheng@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: initialize IP offset for sienna_cichlid (v2)</title>
<updated>2020-06-03T17:52:00+00:00</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2019-11-07T08:28:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=dccdbf3f969033383ac2fbbb64441d89e2de4113'/>
<id>urn:sha1:dccdbf3f969033383ac2fbbb64441d89e2de4113</id>
<content type='text'>
Add IP offset headers and state.

V2: squash in updates (Alex)

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: initialize reg base for navi12</title>
<updated>2019-08-02T15:30:39+00:00</updated>
<author>
<name>Xiaojie Yuan</name>
<email>xiaojie.yuan@amd.com</email>
</author>
<published>2019-05-14T07:22:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=03d0a073cf3f8eced0e27774f15b700a85c9f976'/>
<id>urn:sha1:03d0a073cf3f8eced0e27774f15b700a85c9f976</id>
<content type='text'>
Set up the register offset map for navi12.

Signed-off-by: Xiaojie Yuan &lt;xiaojie.yuan@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/soc15: initialize reg base for navi14 (v2)</title>
<updated>2019-07-18T19:17:58+00:00</updated>
<author>
<name>Xiaojie Yuan</name>
<email>xiaojie.yuan@amd.com</email>
</author>
<published>2018-12-17T10:24:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a0f6d926f139d6fe20ca39f4a27ba0c51458bfd1'/>
<id>urn:sha1:a0f6d926f139d6fe20ca39f4a27ba0c51458bfd1</id>
<content type='text'>
Initialize the IP register base offsets for navi14.

v2: squash in MP, CLK, THM updates

Signed-off-by: Xiaojie Yuan &lt;xiaojie.yuan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add navi10 common ip block (v3)</title>
<updated>2019-06-21T23:59:23+00:00</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2019-03-04T06:07:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c6b6a42175f5d36d8e7f85afb8acb6559210641e'/>
<id>urn:sha1:c6b6a42175f5d36d8e7f85afb8acb6559210641e</id>
<content type='text'>
This adds the core SOC code for navi asics.

v1: add place holder and initial basic function (Ray)
v2: add new introduced functions to avoid reference
    NULL pointer (Hawking)
v3L squash in updates (Alex)

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
