<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/nv.c, branch v6.1.168</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2025-03-28T20:59:01+00:00</updated>
<entry>
<title>drm/amdgpu: Fix JPEG video caps max size for navi1x and raven</title>
<updated>2025-03-28T20:59:01+00:00</updated>
<author>
<name>David Rosca</name>
<email>david.rosca@amd.com</email>
</author>
<published>2025-02-28T12:34:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a94ad20b077972af1935217bddcd1ad6fbe41c37'/>
<id>urn:sha1:a94ad20b077972af1935217bddcd1ad6fbe41c37</id>
<content type='text'>
commit ec33964d9d88488fa954a03d476a8b811efc6e85 upstream.

8192x8192 is the maximum supported resolution.

Signed-off-by: David Rosca &lt;david.rosca@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Ruijing Dong &lt;ruijing.dong@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 6e0d2fde3ae8fdb5b47e10389f23ed2cb4daec5d)
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi</title>
<updated>2023-03-30T10:49:27+00:00</updated>
<author>
<name>Kai-Heng Feng</name>
<email>kai.heng.feng@canonical.com</email>
</author>
<published>2023-03-15T12:07:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ed6364fb7c407ca53447d8b0723a61d320bcbae9'/>
<id>urn:sha1:ed6364fb7c407ca53447d8b0723a61d320bcbae9</id>
<content type='text'>
commit 2b072442f4962231a8516485012bb2d2551ef2fe upstream.

S2idle resume freeze can be observed on Intel ADL + AMD WX5500. This is
caused by commit 0064b0ce85bb ("drm/amd/pm: enable ASPM by default").

The root cause is still not clear for now.

So extend and apply the ASPM quirk from commit e02fe3bc7aba
("drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems"), to
workaround the issue on Navi cards too.

Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default")
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2458
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix error checking in amdgpu_read_mm_registers for nv</title>
<updated>2023-03-17T07:50:15+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-03-07T13:59:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d07d152d762d746016f546f9fedd3f319870cf5e'/>
<id>urn:sha1:d07d152d762d746016f546f9fedd3f319870cf5e</id>
<content type='text'>
commit b42fee5e0b44344cfe4c38e61341ee250362c83f upstream.

Properly skip non-existent registers as well.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>amdgpu/nv.c: Corrected typo in the video capabilities resolution</title>
<updated>2022-12-31T12:32:19+00:00</updated>
<author>
<name>Veerabadhran Gopalakrishnan</name>
<email>veerabadhran.gopalakrishnan@amd.com</email>
</author>
<published>2022-11-23T14:40:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=dba7d85722243638d5f7df7fd2ab02957c412f0b'/>
<id>urn:sha1:dba7d85722243638d5f7df7fd2ab02957c412f0b</id>
<content type='text'>
[ Upstream commit 65009bf2b4d287ef7ad7e6eb082b7c3d35eb611f ]

Corrected the typo in the 4K resolution parameters.

Fixes: b3a24461f9fb15 ("amdgpu/nv.c - Added codec query for Beige Goby")
Fixes: 9075096b09e590 ("amdgpu/nv.c - Optimize code for video codec support structure")
Fixes: 9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query")

Signed-off-by: Veerabadhran Gopalakrishnan &lt;veerabadhran.gopalakrishnan@amd.com&gt;
Acked-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update VCN codec support for Yellow Carp</title>
<updated>2022-06-01T19:56:49+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-05-26T20:34:55+00:00</published>
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<id>urn:sha1:97e50305542f384741a5b45699aba349fe9fca73</id>
<content type='text'>
Supports AV1.  Mesa already has support for this and
doesn't rely on the kernel caps for yellow carp, so
this was already working from an application perspective.

Fixes: 554398174d98 ("amdgpu/nv.c - Added video codec support for Yellow Carp")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2002
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: simplify nv and soc21 read_register functions</title>
<updated>2022-05-06T20:56:57+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-05-05T03:24:00+00:00</published>
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<id>urn:sha1:bf1781e17f30a594f959671af59a253e9313a9b9</id>
<content type='text'>
Check of the base offset for the IP exists rather than
explicitly checking for how many instances of a particular
IP there are.  This is what soc15.c already does.  Expand
this to nv.c and soc21.c.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: correct cp doorbell range</title>
<updated>2022-05-04T14:43:53+00:00</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2022-04-12T20:17:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=fd0ed91ae8a2b5f3d61a6356b6aaeb2f5b097950'/>
<id>urn:sha1:fd0ed91ae8a2b5f3d61a6356b6aaeb2f5b097950</id>
<content type='text'>
1. move MES doorbell inside the mec doorbell range,
   for mes belongs to mec block
2. setting the correct gfx/mec doorbell range, so that
   fw can correctly detect gfx/compute work load to enter/exit
   power saving state.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Tested-and-acked-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: allocate doorbell index for mes kiq</title>
<updated>2022-05-04T14:43:49+00:00</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2021-04-14T08:22:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b608e785e1ed7c665b4eeff79e267322eff3c847'/>
<id>urn:sha1:b608e785e1ed7c665b4eeff79e267322eff3c847</id>
<content type='text'>
Allocate a doorbell index for mes kiq queue.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: expand cg_flags from u32 to u64</title>
<updated>2022-04-08T21:24:24+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2022-03-25T10:00:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=25faeddcf3c3f31f9f43de5c55f7cbdd13d3ebc7'/>
<id>urn:sha1:25faeddcf3c3f31f9f43de5c55f7cbdd13d3ebc7</id>
<content type='text'>
With this, we can support more CG flags.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable gfx power gating for GC 10.3.7</title>
<updated>2022-03-02T23:40:06+00:00</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2022-03-01T06:08:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=fabe1753851c62d0292a39d89a4a8d7f15c96794'/>
<id>urn:sha1:fabe1753851c62d0292a39d89a4a8d7f15c96794</id>
<content type='text'>
Enable gfx power gating for GC 10.3.7.

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
