kernel/linux.git/drivers/gpu/drm/amd/amdgpu/nv.c, branch v5.5.13Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v5.5.132020-02-24T07:38:05+00:00drm/amdgpu/sriov: workaround on rev_id for Navi12 under sriov2020-02-24T07:38:05+00:00Tiecheng ZhouTiecheng.Zhou@amd.com2020-01-08T05:44:29+00:00urn:sha1:6fe61eeb6af192fe246ef4a0baa8e51d878d1ebf
[ Upstream commit df5e984c8bd414561c320d6cbbb66d53abf4c7e2 ]
guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
as a consequence, the rev_id and external_rev_id are wrong.
workaround it by hardcoding the rev_id to 0, which is the default value.
v2. add comment in the code
Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amdgpu/nv: add asic func for fetching vbios from rom directly2019-11-22T19:35:10+00:00Alex Deucheralexander.deucher@amd.com2019-11-13T19:27:54+00:00urn:sha1:f8a69a8022a2aafe534c44f421534909869e619e
Needed as a fallback if the vbios can't be fetched by other means.
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fix sysfs interface pcie_replay_count error on navi asic2019-11-07T23:08:07+00:00Kevin Wangkevin1.wang@amd.com2019-11-05T10:53:30+00:00urn:sha1:2af8153126e1cdd93891a9edef76fbbd497e90ab
the asic callback function of get_pcie_replay_count is not implement on navi asic,
it will cause null pinter error when read this interface.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/SRIOV: SRIOV VF doesn't support BACO2019-10-30T15:06:51+00:00Jiange ZhaoJiange.Zhao@amd.com2019-10-28T10:04:14+00:00urn:sha1:b4def3744ba811f5abc53750c71c52d71a2032b1
SRIOV VF doesn't support BACO.
Only PF with BACO capability can do it.
Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Allow reading more status registers on si/cik2019-10-25T20:50:10+00:00Marek Olšákmarek.olsak@amd.com2019-10-22T21:22:38+00:00urn:sha1:664fe85a2d9283c30044d821c708860999c52f28
Allow userspace to read the same status registers for every family.
Based on commit c7890fea, added any of these registers if defined in
the include files of each architecture.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: don't increment vram lost if we are in hibernation2019-10-03T14:11:05+00:00Alex Deucheralexander.deucher@amd.com2019-10-01T21:45:27+00:00urn:sha1:2c9a0c66d520c94d157d0882b2977a219846845c
We reset the GPU as part of our hibernation sequence so we need
to make sure we don't mark vram as lost in that case.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add the HDP flush support for Navi2019-10-03T14:11:05+00:00Yong ZhaoYong.Zhao@amd.com2019-09-28T03:30:05+00:00urn:sha1:923c087a1f1e51fd6534ad1e4c1650216423679e
The HDP flush support code was missing in the nbio and nv files.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/SRIOV: Navi10/12 VF doesn't support SMU2019-09-16T15:16:14+00:00Jiange ZhaoJiange.Zhao@amd.com2019-09-12T05:15:35+00:00urn:sha1:a4ac7693f8950b6a9be59dcde42fbe103d714dc7
In SRIOV case, SMU and powerplay are handled in HV.
VF shouldn't have control over SMU and powerplay.
Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions2019-09-16T15:15:20+00:00Jiange ZhaoJiange.Zhao@amd.com2019-09-11T09:29:07+00:00urn:sha1:b05b69036f7499d7f3cb52554f3e3dad9fefe00c
Mailbox functions and interrupts are only for Navi12 VF.
Register functions and irqs during initialization.
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: switch to new amdgpu_nbio structure2019-09-13T22:11:03+00:00Hawking ZhangHawking.Zhang@amd.com2019-08-23T11:39:18+00:00urn:sha1:bebc076285458ca6caa3246aa9c13ac062e14835
no functional change, just switch to new structures
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>