kernel/linux.git/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c, branch v6.18.21Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.18.212025-12-18T13:02:41+00:00drm/amdgpu/userq: fix SDMA and compute validation2025-12-18T13:02:41+00:00Alex Deucheralexander.deucher@amd.com2025-10-10T19:21:02+00:00urn:sha1:3e3cb76251769af696907e83a2101676eaac0044
[ Upstream commit a0559012a18a5a6ad87516e982892765a403b8ab ]
The CSA and EOP buffers have different alignement requirements.
Hardcode them for now as a bug fix. A proper query will be added in
a subsequent patch.
v2: verify gfx shadow helper callback (Prike)
Fixes: 9e46b8bb0539 ("drm/amdgpu: validate userq buffer virtual address and size")
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amdgpu: add userq object va track helpers2025-12-18T13:02:41+00:00Prike LiangPrike.Liang@amd.com2025-09-29T05:52:13+00:00urn:sha1:77ac34b838e2093d498e6dc9f5944038ba83c06d
[ Upstream commit 5cfa33fabf01f2cc0af6b1feed6e65cb81806a37 ]
Add the userq object virtual address list_add() helpers
for tracking the userq obj va address usage.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: a0559012a18a ("drm/amdgpu/userq: fix SDMA and compute validation")
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amdgpu: fix hung reset queue array memory allocation2025-10-13T18:14:28+00:00Jonathan Kimjonathan.kim@amd.com2025-10-09T15:28:19+00:00urn:sha1:0ef930e1faca6418316e5b9a3b4d1f6ae9e5b240
By design the MES will return an array result that is twice the number
of hung doorbells it can report.
i.e. if up k reported doorbells are supported, then the
second half of the array, also of length k, holds the HQD information
(type/queue/pipe) where queue 1 corresponds to index 0 and k,
queue 2 corresponds to index 1 and k + 1 etc ...
The driver will use the HDQ info to target queue/pipe reset for
hardware scheduled user compute queues.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: adjust MES API used for suspend and resume2025-09-15T21:02:28+00:00Jesse.ZhangJesse.Zhang@amd.com2025-09-04T08:30:08+00:00urn:sha1:5cefcbb306d6b4fa3ac5fba86db94cac81f0b457
Use the suspend and resume API rather than remove queue
and add queue API. The former just preempts the queue
while the latter remove it from the scheduler completely.
There is no need to do that, we only need preemption
in this case.
V2: replace queue_active with queue state
v3: set the suspend_fence_addr
v4: allocate another per queue buffer for the suspend fence, and set the sequence number.
also wait for the suspend fence. (Alex)
v5: use a wb slot (Alex)
v6: Change the timeout period. For MES, the default timeout is 2100000; /* 2100 ms */ (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: validate userq buffer virtual address and size2025-09-15T20:52:15+00:00Prike LiangPrike.Liang@amd.com2025-06-23T08:29:38+00:00urn:sha1:9e46b8bb0539d7bc9a9e7b3072fa4f6082490392
It needs to validate the userq object virtual address to
determine whether it is residented in a valid vm mapping.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: validate userq input args2025-09-09T20:17:57+00:00Prike LiangPrike.Liang@amd.com2025-05-14T04:43:57+00:00urn:sha1:219be4711a1ba788bc2a9fafc117139d133e5fea
This will help on validating the userq input args, and
rejecting for the invalid userq request at the IOCTLs
first place.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/userq: add a detect and reset callback2025-09-05T21:38:39+00:00Jesse.ZhangJesse.Zhang@amd.com2025-09-04T01:54:36+00:00urn:sha1:54d18bc6003fad33eb901aa5fa3425449e53d5aa
Add a detect and reset callback and add the implementation
for mes. The callback will detect all hung queues of a
particular ip type (e.g., GFX or compute or SDMA) and
reset them.
v2: increase reset counter and set fence force completion
v3: Removed userq_mutex in mes_userq_detect_and_reset since the driver holds it when calling
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/userq: use consistent function naming2025-04-22T12:51:46+00:00Alex Deucheralexander.deucher@amd.com2025-04-16T21:49:45+00:00urn:sha1:42a66677805d03df9e2600fab82d0cbe855500e1
s/userqueue/userq/
1. remove the mix of amdgpu_userqueue and amdgpu_userq
2. to be consistent with other amdgpu_userq_fence.c
3. it's shorter
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: switch from queue_active to queue state2025-04-22T12:51:45+00:00Alex Deucheralexander.deucher@amd.com2025-04-12T16:59:38+00:00urn:sha1:e67b95f0cd5e8dd57a9df5d5d15da6ba7847808a
Track the state of the queue rather than simple active vs
not. This is needed for other states (hung, preempted, etc.).
While we are at it, move the state tracking into the user
queue front end code.
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/userq/mes: pass the secure flag to mqd init2025-04-22T12:51:44+00:00Alex Deucheralexander.deucher@amd.com2025-02-27T02:25:22+00:00urn:sha1:87ceff6136dbbfc8d530a1be7e3ba1282548d6dc
So that we initialize the MQD as a secure queue.
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Jesse.Zhang <Jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>