<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/cik.c, branch v6.6.132</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.132</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.132'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-08-21T19:11:35+00:00</updated>
<entry>
<title>drm/amdgpu: Use RMW accessors for changing LNKCTL</title>
<updated>2023-08-21T19:11:35+00:00</updated>
<author>
<name>Ilpo Järvinen</name>
<email>ilpo.jarvinen@linux.intel.com</email>
</author>
<published>2023-07-17T12:04:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ce7d88110b9ed5f33fe79ea6d4ed049fb0e57bce'/>
<id>urn:sha1:ce7d88110b9ed5f33fe79ea6d4ed049fb0e57bce</id>
<content type='text'>
Don't assume that only the driver would be accessing LNKCTL. ASPM policy
changes can trigger write to LNKCTL outside of driver's control.  And in
the case of upstream bridge, the driver does not even own the device it's
changing the registers for.

Use RMW capability accessors which do proper locking to avoid losing
concurrent updates to the register value.

Suggested-by: Lukas Wunner &lt;lukas@wunner.de&gt;
Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts")
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Link: https://lore.kernel.org/r/20230717120503.15276-6-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add xcc index argument to select_sh_se function v2</title>
<updated>2023-04-18T20:28:55+00:00</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2022-05-24T03:22:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d51ac6d0a23caf1005cb640f8533161c5d2dd0c0'/>
<id>urn:sha1:d51ac6d0a23caf1005cb640f8533161c5d2dd0c0</id>
<content type='text'>
v1: To support multiple XCD case (Le)
v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking)

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Refactor `amdgpu_aspm` to be evaluated per device</title>
<updated>2022-02-17T20:59:05+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2022-02-17T05:19:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0ab5d711ec74d9e60673900974806b7688857947'/>
<id>urn:sha1:0ab5d711ec74d9e60673900974806b7688857947</id>
<content type='text'>
Evaluating `pcie_aspm_enabled` as part of driver probe has the implication
that if one PCIe bridge with an AMD GPU connected doesn't support ASPM
then none of them do.  This is an invalid assumption as the PCIe core will
configure ASPM for individual PCIe bridges.

Create a new helper function that can be called by individual dGPUs to
react to the `amdgpu_aspm` module parameter without having negative results
for other dGPUs on the PCIe bus.

Suggested-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: don't do resets on APUs which don't support it</title>
<updated>2022-01-14T23:06:44+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-01-13T03:38:51+00:00</published>
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<id>urn:sha1:e8309d50e97851ff135c4e33325d37b032666b94</id>
<content type='text'>
It can cause a hang.  This is normally not enabled for GPU
hangs on these asics, but was recently enabled for handling
aborted suspends.  This causes hangs on some platforms
on suspend.

Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)")
Cc: stable@vger.kernel.org
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1858
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3)</title>
<updated>2021-08-06T01:17:58+00:00</updated>
<author>
<name>Ryan Taylor</name>
<email>Ryan.Taylor@amd.com</email>
</author>
<published>2021-06-18T20:16:37+00:00</published>
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<id>urn:sha1:733ee71ae0d03a8b03711dca8bc94c8ac05a6bc3</id>
<content type='text'>
Move dce_virtual into amdgpu_vkms and update all references to
dce_virtual with amdgpu_vkms.

v2: Removed more references to dce_virtual.

v3: Restored display modes from previous implementation.

Signed-off-by: Ryan Taylor &lt;Ryan.Taylor@amd.com&gt;
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/codec: drop the internal codec index</title>
<updated>2021-02-26T22:23:49+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-02-02T16:11:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6f786950b1ff051c6dd913b1bb3aaa9b57befcbf'/>
<id>urn:sha1:6f786950b1ff051c6dd913b1bb3aaa9b57befcbf</id>
<content type='text'>
And just use the ioctl index.  They are the same.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3)</title>
<updated>2021-02-26T22:23:49+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-01-07T23:48:12+00:00</published>
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<id>urn:sha1:3b246e8b6a97b7786f49433effea2aff39e58166</id>
<content type='text'>
For each asic family.  Will be used to populate tables
for the new INFO ioctl query.

v2: add max_pixels_per_frame to handle the portrait case
v3: fix copy paste typos

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt; (v1)
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/cik: minor clean up of reset code</title>
<updated>2021-02-09T20:29:50+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-02-04T15:38:13+00:00</published>
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<id>urn:sha1:44ab8bb0bb63feedd59afdda83218a608fd9780a</id>
<content type='text'>
Drop duplicate reset method logging, whitespace changes.

Acked-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/cik: enable BACO reset on Bonaire</title>
<updated>2020-12-09T04:06:23+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-12-04T18:08:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=580577fbb4f559a46c27b655d1854950cb5b29ea'/>
<id>urn:sha1:580577fbb4f559a46c27b655d1854950cb5b29ea</id>
<content type='text'>
Works now that the BACO sequence is fixed.

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: enable baco reset for Hawaii</title>
<updated>2020-10-30T05:00:36+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-10-28T07:37:00+00:00</published>
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<id>urn:sha1:0134022fa3ab0e082bb821a81ef2ffa7027ebd10</id>
<content type='text'>
Which can be used for S4(hibernation) support.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Tested-by: Sandeep Raghuraman &lt;sandy.8925@gmail.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
