kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c, branch v7.2-rc1

drm/amdgpu: restructure VM state machine v4

2026-05-19T15:54:32+00:00

Instead of coming up with more sophisticated names for states a VM BO can be in, group them by the type of BO first and then by the state. So we end with BO type kernel, always_valid and individual and then states evicted, moved and idle. Not much functional change, except that evicted_user is moved back together with the other BOs again which makes the handling in amdgpu_vm_validate() a bit more complex. Also fixes a problem with user queues and amdgpu_vm_ready(). We didn't considered the VM ready when user BOs were not ideally placed, harmless performance impact for kernel queues but a complete show stopper for userqueues. v2: fix a few typos in comments, rename the BO types to make them more descriptive, fix a couple of bugs found during testing v3: squashed together with revert to old status lock handling, looks like the first patch still had some bug which this one here should fix. Fix a missing lock around debugfs printing. v4: fix merge clash pointed out by Prike Signed-off-by: Christian König Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher

drm/amdgpu: Move VM PTE MTYPE override to per-PTE granularity

2026-04-28T18:42:22+00:00

Refactor the NUMA-aware MTYPE override for VM page table entries: Move the override_vm_pte_flags call from the centralized amdgpu_vm_pte_update_flags() into the individual CPU and SDMA update backends, enabling per-PTE MTYPE override including for scattered pages (pages_addr path). Move APU, IP version, and direct-mapped eligibility checks from runtime (gmc_v9_0_override_vm_pte_flags) to init time (gmc_v9_0_set_gmc_funcs), to avoid repeated runtime checks on every PTE update. Signed-off-by: Philip Yang Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: OR init_pte_flags into invalid leaf PTE updates

2026-04-21T20:54:45+00:00

Invalid leaf clears that only set AMDGPU_PTE_EXECUTABLE match the old GMC9 fault-priority workaround but omit adev->gmc.init_pte_flags. On GFX12 that includes AMDGPU_PTE_IS_PTE; without it, some cleared PTEs can fault as no-retry and bypass the SVM/XNACK handler when a VA is reused after a BO unmap. Apply init_pte_flags in amdgpu_vm_pte_update_flags() alongside EXECUTABLE so range-driven clears (e.g. amdgpu_vm_clear_freed) match amdgpu_vm_pt_clear() for leaf templates. Signed-off-by: Siwei He Reviewed-by: Philip Yang Signed-off-by: Alex Deucher

Revert "drm/amdgpu: revert to old status lock handling v4"

2026-03-17T14:28:47+00:00

This reverts commit 7a9419ab42699fd3d4c857ef81ae097d8d8d5899. Reverting due to some of the probable issues caused by this change and CI is blocked. Signed-off-by: Sunil Khatri Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: revert to old status lock handling v4

2026-03-11T17:58:08+00:00

It turned out that protecting the status of each bo_va with a spinlock was just hiding problems instead of solving them. Revert the whole approach, add a separate stats_lock and lockdep assertions that the correct reservation lock is held all over the place. This not only allows for better checks if a state transition is properly protected by a lock, but also switching back to using list macros to iterate over the state of lists protected by the dma_resv lock of the root PD. v2: re-add missing check v3: split into two patches v4: re-apply by fixing holding the VM lock at the right places. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher

drm/amdgpu: Add per-ASIC PTE init flag

2025-12-08T18:56:35+00:00

On GFX12.1, default PTE setup needs an additional bit to be set. Add PTE initialization flags to handle setup default PTE on a per-ASIC basis. While at it, fixup the coding style too. Signed-off-by: Mukul Joshi Reviewed-by: Philip Yang Signed-off-by: Alex Deucher

drm/amdgpu: GPU vm support 5-level page table

2025-12-08T18:56:30+00:00

If GPU supports 5-level page table, but CPU disable 5-level page table by using boot option no5lvl or CPU feature not available, the virtual address will be 48bit, not needed to enable 5-level page table on GPU vm. If adev->vm_manager.num_level, number of pde levels, set to 4, then gfxhub and mmhub register VM_CONTEXTx_CNTL/PAGE_TABLE_DEPTH will set to 4 to enable 5-level page table in page table walker. Set vm_manager.root_level to AMDGPU_VM_PDE3, then update GPU mapping will allocate and update PDE3/PDE2/PDE1/PDE0/PTB 5-level page tables. If max_level is not 4, no change for the logic to support features needed by old ASICs. v2: squash in CONFIG fix Signed-off-by: Philip Yang Acked-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: partially revert "revert to old status lock handling v3"

2025-10-07T18:09:19+00:00

The CI systems are pointing out list corruptions, so we still need to fix something here. Keep the asserts, but revert the lock changes for now. Fixes: 59e4405e9ee2 ("drm/amdgpu: revert to old status lock handling v3") Signed-off-by: Christian König Acked-by: Alex Deucher Signed-off-by: Alex Deucher

Merge tag 'amd-drm-next-6.18-2025-09-19' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

2025-09-21T22:45:51+00:00

amd-drm-next-6.18-2025-09-19: amdgpu: - Fence drv clean up fix - DPC fixes - Misc display fixes - Support the MMIO remap page as a ttm pool - JPEG parser updates - UserQ updates - VCN ctx handling fixes - Documentation updates - Misc cleanups - SMU 13.0.x updates - SI DPM updates - GC 11.x cleaner shader updates - DMCUB updates - DML fixes - Improve fallback handling for pixel encoding - VCN reset improvements - DCE6 DC updates - DSC fixes - Use devm for i2c buses - GPUVM locking updates - GPUVM documentation improvements - Drop non-DC DCE11 code - S0ix fixes - Backlight fix - SR-IOV fixes amdkfd: - SVM updates Signed-off-by: Dave Airlie From: Alex Deucher Link: https://lore.kernel.org/r/20250919193354.2989255-1-alexander.deucher@amd.com

drm/amdgpu: revert to old status lock handling v3

2025-09-18T20:59:14+00:00

It turned out that protecting the status of each bo_va with a spinlock was just hiding problems instead of solving them. Revert the whole approach, add a separate stats_lock and lockdep assertions that the correct reservation lock is held all over the place. This not only allows for better checks if a state transition is properly protected by a lock, but also switching back to using list macros to iterate over the state of lists protected by the dma_resv lock of the root PD. v2: re-add missing check v3: split into two patches Signed-off-by: Christian König Acked-by: Sunil Khatri Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher