<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c, branch v6.6.36</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.36</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.36'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-08-09T13:43:47+00:00</updated>
<entry>
<title>drm/amdgpu: Clean up errors in amdgpu_virt.c</title>
<updated>2023-08-09T13:43:47+00:00</updated>
<author>
<name>Ran Sun</name>
<email>sunran001@208suo.com</email>
</author>
<published>2023-08-02T07:31:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=baa5ede87568677b6321f9559b7bc2a16acb3f10'/>
<id>urn:sha1:baa5ede87568677b6321f9559b7bc2a16acb3f10</id>
<content type='text'>
Fix the following errors reported by checkpatch:

ERROR: space required before the open parenthesis '('

Signed-off-by: Ran Sun &lt;sunran001@208suo.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: load sdma ucode in the guest machine</title>
<updated>2023-07-25T17:47:26+00:00</updated>
<author>
<name>YuanShang</name>
<email>YuanShang.Mao@amd.com</email>
</author>
<published>2023-06-30T08:40:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=30b59910d9d003424ae1dc327070ad59195c87b2'/>
<id>urn:sha1:30b59910d9d003424ae1dc327070ad59195c87b2</id>
<content type='text'>
[why]
User mode driver need to check the sdma ucode version to
see whether the sdma engine supports a new type of PM4 packet.
In SRIOV, sdma is loaded by the host. And, there is no way
to check the sdma ucode version of CHIP_NAVI12 and
CHIP_SIENNA_CICHLID of the host in the guest machine.

[how]
Load the sdma ucode for CHIP_NAVI12 and CHIP_SIENNA_CICHLID
in the guest machine.

Signed-off-by: YuanShang &lt;YuanShang.Mao@amd.com&gt;
Reviewed-By: Horace Chen &lt;horace.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: set sw state to gfxoff after SR-IOV reset</title>
<updated>2023-07-25T17:35:23+00:00</updated>
<author>
<name>Horace Chen</name>
<email>horace.chen@amd.com</email>
</author>
<published>2023-07-19T07:55:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=83f24a8f0532f6d9fcdbe36e438f00a1a082fcd4'/>
<id>urn:sha1:83f24a8f0532f6d9fcdbe36e438f00a1a082fcd4</id>
<content type='text'>
[Why]
Current SR-IOV will not set GC to off state, while it is a real
GC hard reset. Whthout GFX off flag, driver may do gfxhub invalidation
before firmware load and gfxhub gart enable. This operation may cause
CP to become busy because GC is not in the right state for invalidation.

[How]
Add a function for SR-IOV to clean up some sw state before recover. Set
adev-&gt;gfx.is_poweron to false to prevent gfxhub invalidation before gfx
firmware autoload complete.

Signed-off-by: Horace Chen &lt;horace.chen@amd.com&gt;
Reviewed-by: HaiJun Chang &lt;HaiJun.Chang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)</title>
<updated>2023-07-18T15:16:41+00:00</updated>
<author>
<name>Victor Lu</name>
<email>victorchengchi.lu@amd.com</email>
</author>
<published>2023-06-16T15:01:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8ed49dd1d3a7448744d57e1da2062b074cba2e49'/>
<id>urn:sha1:8ed49dd1d3a7448744d57e1da2062b074cba2e49</id>
<content type='text'>
Add RLCG interface support for gfx v9.4.3 and multiple XCCs.
Do not enable it yet.

v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs
    in amdgpu_mm_wreg_mmio_rlc

v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl

Signed-off-by: Victor Lu &lt;victorchengchi.lu@amd.com&gt;
Reviewed-by: Zhigang Luo &lt;zhigang.luo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: make mcbp a per device setting</title>
<updated>2023-06-30T17:12:14+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-06-16T20:49:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=02ff519e99fc90f6c9aed50def1b6d65e20c1875'/>
<id>urn:sha1:02ff519e99fc90f6c9aed50def1b6d65e20c1875</id>
<content type='text'>
So we can selectively enable it on certain devices.  No
intended functional change.

Reviewed-and-tested-by: Jiadong Zhu &lt;Jiadong.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add the accelerator PCIe class</title>
<updated>2023-06-09T16:48:57+00:00</updated>
<author>
<name>Shiwu Zhang</name>
<email>shiwu.zhang@amd.com</email>
</author>
<published>2023-05-23T04:02:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9d65b1b4bcf3918164e17365eec169875eef8ee3'/>
<id>urn:sha1:9d65b1b4bcf3918164e17365eec169875eef8ee3</id>
<content type='text'>
Add the accelerator PCIe class and match the
class in amdgpu for 0x1002 devices of that class.

From PCI spec:
"PCI Code and ID Assignment, r1.9, sec 1, 1.19"

Signed-off-by: Shiwu Zhang &lt;shiwu.zhang@amd.com&gt;
Acked-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;  # pci_ids.h
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: disable virtual display support on APP device</title>
<updated>2023-06-09T16:47:31+00:00</updated>
<author>
<name>Yang Wang</name>
<email>kevinyang.wang@amd.com</email>
</author>
<published>2023-06-05T03:39:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=731b48463b0d96eda1f1684eacde6e9c8065df83'/>
<id>urn:sha1:731b48463b0d96eda1f1684eacde6e9c8065df83</id>
<content type='text'>
virtual display is not support on APP device.

Signed-off-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Signed-off-by: Gavin Wan &lt;gavin.wan@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Remove IMU ucode in vf2pf</title>
<updated>2023-06-09T14:41:07+00:00</updated>
<author>
<name>YuanShang</name>
<email>YuanShang.Mao@amd.com</email>
</author>
<published>2023-05-08T04:12:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c77b3608b8ec79a33ac36a9d281e0395a3343d6e'/>
<id>urn:sha1:c77b3608b8ec79a33ac36a9d281e0395a3343d6e</id>
<content type='text'>
The IMU firmware is loaded on the host side, not the guest.
Remove IMU in vf2pf ucode id enum.

Signed-off-by: YuanShang &lt;YuanShang.Mao@amd.com&gt;
Reviewed-By: Horace Chen &lt;horace.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: set default num_kcq to 2 under sriov</title>
<updated>2023-06-09T13:34:35+00:00</updated>
<author>
<name>YuBiao Wang</name>
<email>YuBiao.Wang@amd.com</email>
</author>
<published>2023-05-05T06:35:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=db5dcd476eb0288cdfa781725582dcf9bd747a6b'/>
<id>urn:sha1:db5dcd476eb0288cdfa781725582dcf9bd747a6b</id>
<content type='text'>
The number of kernel queues has impact on the latency under sriov
usecase. So to reduce the latency we set the default num_kcq = 2 under
sriov if not set manually.

Signed-off-by: YuBiao Wang &lt;YuBiao.Wang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable mcbp under sriov by default</title>
<updated>2023-06-09T13:25:50+00:00</updated>
<author>
<name>YuBiao Wang</name>
<email>YuBiao.Wang@amd.com</email>
</author>
<published>2023-04-28T06:00:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d446127107e8185c2dc750cd4d0c5ff697a694f6'/>
<id>urn:sha1:d446127107e8185c2dc750cd4d0c5ff697a694f6</id>
<content type='text'>
Enable mcbp under sriov by default. Asics with soc21 supports mcbp now
so we should set it enabled.

Signed-off-by: YuBiao Wang &lt;YuBiao.Wang@amd.com&gt;
Reviewed-by: Horace Chen &lt;horace.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
