kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c, branch v5.16.1Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v5.16.12021-10-28T18:26:12+00:00drm/amdgpu: Update TA version output in driver2021-10-28T18:26:12+00:00Candice Licandice.li@amd.com2021-10-21T06:52:59+00:00urn:sha1:4320e6f86d976f86d836441c31e23ef8cfed048e
TA version should only be displayed in firmware version column.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add dummy_page_addr to sriov msg2021-10-22T03:38:16+00:00Jingwen ChenJingwen.Chen2@amd.com2021-10-21T08:46:14+00:00urn:sha1:e77f0f5c6a66298b034c8e2021c5a0ece07235ac
Add dummy_page_addr to sriov msg for host driver to set
GCVM_L2_PROTECTION_DEFAULT_ADDR* registers correctly.
v2:
should update vf2pf msg instead
Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Reviewed-by: Horace Chen <horace.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Unify PSP TA context2021-09-14T19:59:58+00:00Candice Licandice.li@amd.com2021-09-08T15:58:59+00:00urn:sha1:de3a1e336057fd12210eead4367205594e5ac991
Remove all TA binary structures and add the specific binary
structure in struct ta_context.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: consolidate PSP TA context2021-08-16T19:18:04+00:00Candice Licandice.li@amd.com2021-08-13T02:14:43+00:00urn:sha1:6457205c07563f1f6b101ff9ef747bd7ed57e4a7
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add consistent PSP FW loading size checking2021-07-23T14:08:00+00:00Candice Licandice.li@amd.com2021-07-21T17:55:59+00:00urn:sha1:222e0a71c2973939c861d84d460edd4e3cf25bed
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: John Clements <John.Clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fill adev->unique_id with data from PF2VF msg2021-05-20T02:33:58+00:00Jiawei GuJiawei.Gu@amd.com2021-05-13T06:17:58+00:00urn:sha1:5228cd65742abd2221d7bdb622544ac47e41d87c
Initialize unique_id from PF2VF under virtualization.
V2: skip smu_get_unique_id() under virtualization
Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Complete multimedia bandwidth interface2021-05-20T02:29:58+00:00Bokun Zhangbokun.zhang@amd.com2021-05-13T05:17:54+00:00urn:sha1:ed9d205363c3ec786126e46568e9e9aadaf0cb93
- Update SRIOV PF2VF header with latest revision
- Extend existing function in amdgpu_virt.c to read MM bandwidth config
from PF2VF message
- Add SRIOV Sienna Cichlid codec array and update the bandwidth with
PF2VF message
v2: squash in removal of unused variable (Alex)
Signed-off-by: Bokun Zhang <bokun.zhang@amd.com>
Reviewed-by: Monk liu <monk.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add Aldebaran virtualization support2021-05-10T22:06:43+00:00Zhigang Luozhigang.luo@amd.com2021-04-29T19:37:31+00:00urn:sha1:e7de0d844ea803d752e0b41e6b7dcc35d671c186
1. add Aldebaran in virtualization detection list.
2. disable Aldebaran virtual display support as there is no GFX
engine in Aldebaran.
3. skip TMR loading if Aldebaran is in virtualizatin mode as it
shares the one host loaded.
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: indirect register access for nv12 sriov2021-04-09T20:50:13+00:00Peng Ju ZhouPengJu.Zhou@amd.com2021-03-30T10:27:15+00:00urn:sha1:5d23851029b78fb6d6d56a40300676d49a0ce609
using the control bits got from host to control registers access.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: indirect register access for nv12 sriov2021-04-09T20:50:09+00:00Peng Ju ZhouPengJu.Zhou@amd.com2021-03-29T07:47:20+00:00urn:sha1:77eabc6f5975dafeb76f7c7c2451282b91e9f5b6
get pf2vf msg info at it's earliest time so that
guest driver can use these info to decide whether
register indirect access enabled.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>