kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c, branch linux-4.20.y

drm/amdgpu/vcn:Correct VCN cache window definition

2018-10-09T22:07:39+00:00

Correct VCN cache window definition. The old one is reused from UVD, and it is not fully correct. Signed-off-by: James Zhu Acked-by: Leo Liu Signed-off-by: Alex Deucher

drm/amdgpu/vcn:Replace value with defined macro

2018-10-09T22:07:33+00:00

Replace value with defined macro to make code more readable Signed-off-by: James Zhu Acked-by: Leo Liu Signed-off-by: Alex Deucher

drm/amdgpu/vcn:fix dpg pause mode hang issue

2018-10-09T22:07:26+00:00

Use mmUVD_SCRATCH2 tracking decode write point. It will help avoid dpg pause mode hang issue. Signed-off-by: James Zhu Acked-by: Leo Liu Signed-off-by: Alex Deucher

BackMerge v4.19-rc6 into drm-next

2018-10-04T01:03:34+00:00

I have some pulls based on rc6, and I prefer to have an explicit backmerge. Signed-off-by: Dave Airlie

drm/amdgpu: Fix vce work queue was not cancelled when suspend

2018-09-27T15:01:20+00:00

The vce cancel_delayed_work_sync never be called. driver call the function in error path. This caused the A+A suspend hang when runtime pm enebled. As we will visit the smu in the idle queue. this will cause smu hang because the dgpu has been suspend, and the dgpu also will be waked up. As the smu has been hang, so the dgpu resume will failed. Reviewed-by: Christian König Reviewed-by: Feifei Xu Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amdgpu/vcn: whitespace cleanup

2018-09-27T02:09:26+00:00

Fix some indentation issues. Reviewed-by: Christian König Reviewed-by: James Zhu Signed-off-by: Alex Deucher

drm/amdgpu:Add DPG pause mode support

2018-09-27T02:09:25+00:00

Add functions to support VCN DPG pause mode. Signed-off-by: James Zhu Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib test

2018-09-27T02:09:23+00:00

Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers can't be directly accessed under DPG(Dynamic Power Gate) mode. Signed-off-by: James Zhu Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: simplify Raven, Raven2, and Picasso handling

2018-09-14T14:38:03+00:00

Treat them all as Raven rather than adding a new picasso asic type. This simplifies a lot of code and also handles the case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu fw handling for picasso. Acked-by: Huang Rui Signed-off-by: Alex Deucher

drm/amdgpu: add raven2 vcn firmware support

2018-09-14T14:36:15+00:00

Specify raven2 vcn firmware on amdgpu_vce_sw_init. Signed-off-by: Feifei Xu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher